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gpu layer refactor progress

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This commit is contained in:
jacob 2025-07-31 22:00:24 -05:00
parent 19c0140868
commit bdac093378
2 changed files with 346 additions and 365 deletions
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416
src/gpu/gpu_dx12.c
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295
src/gpu/gpu_dx12.h
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@ -51,19 +51,38 @@
* structs
* ========================== */
struct shader_desc
Struct(GPU_D12_Descriptor)
{
String file;
String func;
struct GPU_D12_CpuDescriptorHeap *heap;
u32 index;
D3D12_CPU_DESCRIPTOR_HANDLE handle;
GPU_D12_Descriptor *next_free;
};
struct pipeline_rtv_desc
Struct(GPU_D12_Resource)
{
enum D3D12_RESOURCE_STATES state;
ID3D12Resource *resource;
GPU_D12_Descriptor *cbv_descriptor;
GPU_D12_Descriptor *srv_descriptor;
GPU_D12_Descriptor *uav_descriptor;
GPU_D12_Descriptor *rtv_descriptor;
D3D12_GPU_VIRTUAL_ADDRESS gpu_address; /* NOTE: 0 for textures */
Vec2I32 texture_size;
GPU_D12_Resource *next_free;
};
Struct(GPU_D12_RtvDesc)
{
DXGI_FORMAT format;
b32 blending;
};
struct pipeline_desc
Struct(GPU_D12_PipelineDesc)
{
String name;
@ -72,10 +91,10 @@ struct pipeline_desc
String ps_dxc;
String cs_dxc;
struct pipeline_rtv_desc rtvs[8];
GPU_D12_RtvDesc rtvs[8];
};
struct pipeline
Struct(GPU_D12_Pipeline)
{
String name;
u64 hash;
@ -89,41 +108,28 @@ struct pipeline
ID3D12PipelineState *pso;
ID3D12RootSignature *rootsig;
struct pipeline_desc desc;
GPU_D12_PipelineDesc desc;
struct pipeline *next;
GPU_D12_Pipeline *next;
};
struct pipeline_error
{
String msg;
struct pipeline_error *next;
};
struct pipeline_include
{
String name;
u64 name_hash;
struct pipeline_include *next;
};
struct pipeline_scope
Struct(GPU_D12_PipelineScope)
{
Arena *arena;
Dict *refs;
struct pipeline_scope *next_free;
GPU_D12_PipelineScope *next_free;
};
struct command_queue_desc
Struct(GPU_D12_CommandQueueDesc)
{
enum D3D12_COMMAND_LIST_TYPE type;
enum D3D12_COMMAND_QUEUE_PRIORITY priority;
String dbg_name;
};
struct command_queue
Struct(GPU_D12_CommandQueue)
{
struct command_queue_desc desc;
GPU_D12_CommandQueueDesc desc;
ID3D12CommandQueue *cq;
Arena *arena;
@ -131,123 +137,98 @@ struct command_queue
u64 submit_fence_target;
ID3D12Fence *submit_fence;
struct command_list_pool *cl_pool;
struct GPU_D12_CommandListPool *cl_pool;
#if ProfilingGpu
__prof_dx12_ctx(prof);
#endif
};
struct command_list_pool
Struct(GPU_D12_CommandListPool)
{
struct command_queue *cq;
GPU_D12_CommandQueue *cq;
Arena *arena;
P_Mutex mutex;
struct command_list *first_submitted_command_list;
struct command_list *last_submitted_command_list;
struct GPU_D12_CommandList *first_submitted_command_list;
struct GPU_D12_CommandList *last_submitted_command_list;
};
struct command_list
{
struct command_queue *cq;
struct command_list_pool *pool;
struct ID3D12CommandAllocator *ca;
struct ID3D12GraphicsCommandList *cl;
P_Lock global_record_lock;
struct pipeline *cur_pipeline;
struct command_descriptor_heap *first_command_descriptor_heap;
struct command_buffer *first_command_buffer;
u64 submitted_fence_target;
struct command_list *prev_submitted;
struct command_list *next_submitted;
};
struct command_descriptor_heap
Struct(GPU_D12_CommandDescriptorHeap)
{
D3D12_DESCRIPTOR_HEAP_TYPE type;
ID3D12DescriptorHeap *heap;
D3D12_CPU_DESCRIPTOR_HANDLE start_cpu_handle;
D3D12_GPU_DESCRIPTOR_HANDLE start_gpu_handle;
struct command_descriptor_heap *next_in_command_list;
GPU_D12_CommandDescriptorHeap *next_in_command_list;
u64 submitted_fence_target;
struct command_queue *submitted_cq;
struct command_descriptor_heap *prev_submitted;
struct command_descriptor_heap *next_submitted;
GPU_D12_CommandQueue *submitted_cq;
GPU_D12_CommandDescriptorHeap *prev_submitted;
GPU_D12_CommandDescriptorHeap *next_submitted;
};
struct command_buffer
Struct(GPU_D12_CommandBuffer)
{
struct command_buffer_group *group;
struct GPU_D12_CommandBufferGroup *group;
u64 size;
struct dx12_resource *resource;
GPU_D12_Resource *resource;
D3D12_VERTEX_BUFFER_VIEW vbv;
D3D12_INDEX_BUFFER_VIEW Ibv;
struct command_buffer *next_in_command_list;
GPU_D12_CommandBuffer *next_in_command_list;
u64 submitted_fence_target;
struct command_queue *submitted_cq;
struct command_buffer *prev_submitted;
struct command_buffer *next_submitted;
GPU_D12_CommandQueue *submitted_cq;
GPU_D12_CommandBuffer *prev_submitted;
GPU_D12_CommandBuffer *next_submitted;
};
struct command_buffer_group
Struct(GPU_D12_CommandBufferGroup)
{
struct command_buffer *first_submitted;
struct command_buffer *last_submitted;
GPU_D12_CommandBuffer *first_submitted;
GPU_D12_CommandBuffer *last_submitted;
};
struct descriptor
Struct(GPU_D12_CommandList)
{
struct cpu_descriptor_heap *heap;
GPU_D12_CommandQueue *cq;
GPU_D12_CommandListPool *pool;
struct ID3D12CommandAllocator *ca;
struct ID3D12GraphicsCommandList *cl;
P_Lock global_record_lock;
u32 index;
D3D12_CPU_DESCRIPTOR_HANDLE handle;
GPU_D12_Pipeline *cur_pipeline;
struct descriptor *next_free;
GPU_D12_CommandDescriptorHeap *first_command_descriptor_heap;
GPU_D12_CommandBuffer *first_command_buffer;
u64 submitted_fence_target;
GPU_D12_CommandList *prev_submitted;
GPU_D12_CommandList *next_submitted;
};
struct dx12_resource
Struct(GPU_D12_SwapchainBuffer)
{
enum D3D12_RESOURCE_STATES state;
struct GPU_D12_Swapchain *swapchain;
ID3D12Resource *resource;
struct descriptor *cbv_descriptor;
struct descriptor *srv_descriptor;
struct descriptor *uav_descriptor;
struct descriptor *rtv_descriptor;
D3D12_GPU_VIRTUAL_ADDRESS gpu_address; /* NOTE: 0 for textures */
Vec2I32 texture_size;
struct dx12_resource *next_free;
};
struct swapchain_buffer
{
struct swapchain *swapchain;
ID3D12Resource *resource;
struct descriptor *rtv_descriptor;
GPU_D12_Descriptor *rtv_descriptor;
D3D12_RESOURCE_STATES state;
};
struct swapchain
Struct(GPU_D12_Swapchain)
{
IDXGISwapChain3 *swapchain;
HWND hwnd;
HANDLE waitable;
Vec2I32 resolution;
struct swapchain_buffer buffers[DX12_SWAPCHAIN_BUFFER_COUNT];
GPU_D12_SwapchainBuffer buffers[DX12_SWAPCHAIN_BUFFER_COUNT];
struct swapchain *next_free;
GPU_D12_Swapchain *next_free;
};
struct cpu_descriptor_heap
Struct(GPU_D12_CpuDescriptorHeap)
{
enum D3D12_DESCRIPTOR_HEAP_TYPE type;
Arena *arena;
@ -257,32 +238,32 @@ struct cpu_descriptor_heap
u32 num_descriptors_reserved;
u32 num_descriptors_capacity;
struct descriptor *first_free_descriptor;
GPU_D12_Descriptor *first_free_descriptor;
ID3D12DescriptorHeap *heap;
struct D3D12_CPU_DESCRIPTOR_HANDLE handle;
};
enum fenced_release_kind
typedef i32 GPU_D12_FencedReleaseKind; enum
{
FENCED_RELEASE_KIND_NONE,
FENCED_RELEASE_KIND_RESOURCE,
FENCED_RELEASE_KIND_PIPELINE
GPU_D12_FencedReleaseKind_None,
GPU_D12_FencedReleaseKind_Resource,
GPU_D12_FencedReleaseKind_Pipeline
};
struct fenced_release_data
Struct(GPU_D12_FencedReleaseData)
{
enum fenced_release_kind kind;
GPU_D12_FencedReleaseKind kind;
void *ptr;
};
struct command_queue_alloc_job_sig { struct command_queue_desc *descs_in; struct command_queue **cqs_out; };
Struct(GPU_D12_AllocCommandQueueJobSig) { GPU_D12_CommandQueueDesc *descs_in; GPU_D12_CommandQueue **cqs_out; };
struct pipeline_alloc_job_sig { struct pipeline_desc *descs_in; struct pipeline **pipelines_out; };
Struct(GPU_D12_AllocPipelineJobSig) { GPU_D12_PipelineDesc *descs_in; GPU_D12_Pipeline **pipelines_out; };
struct dx12_upload_job_sig { struct dx12_resource *resource; void *data; };
Struct(GPU_D12_UploadJobSig) { GPU_D12_Resource *resource; void *data; };
struct shader_compile_desc
Struct(GPU_D12_ShaderDesc)
{
String src;
String friendly_name;
@ -290,7 +271,7 @@ struct shader_compile_desc
String target;
};
struct shader_compile_result
Struct(GPU_D12_CompiledShaderResult)
{
i64 elapsed_ns;
String dxc;
@ -298,15 +279,15 @@ struct shader_compile_result
b32 success;
};
struct shader_compile_job_sig
Struct(GPU_D12_CompileShaderJobSig)
{
Arena *arena;
struct shader_compile_desc *descs;
struct shader_compile_result *results;
GPU_D12_ShaderDesc *descs;
GPU_D12_CompiledShaderResult *results;
};
struct render_sig
Struct(GPU_D12_RenderSig)
{
Arena *arena;
RandState rand;
@ -329,16 +310,16 @@ struct render_sig
Arena *material_grid_descs_arena;
/* Resources */
struct dx12_resource *albedo;
struct dx12_resource *emittance;
struct dx12_resource *emittance_flood_read;
struct dx12_resource *emittance_flood_target;
struct dx12_resource *shade_read;
struct dx12_resource *shade_target;
struct dx12_resource *ui_target;
GPU_D12_Resource *albedo;
GPU_D12_Resource *emittance;
GPU_D12_Resource *emittance_flood_read;
GPU_D12_Resource *emittance_flood_target;
GPU_D12_Resource *shade_read;
GPU_D12_Resource *shade_target;
GPU_D12_Resource *ui_target;
};
struct material_instance_desc
Struct(GPU_D12_MaterialInstanceDesc)
{
Xform xf;
u32 texture_id;
@ -349,7 +330,7 @@ struct material_instance_desc
u32 grid_id;
};
struct ui_rect_instance_desc
Struct(GPU_D12_UiRectInstanceDesc)
{
Xform xf;
u32 texture_id;
@ -357,7 +338,7 @@ struct ui_rect_instance_desc
u32 tint;
};
struct material_grid_desc
Struct(GPU_D12_MaterialGridDesc)
{
f32 line_thickness;
f32 line_spacing;
@ -380,8 +361,8 @@ Struct(GPU_D12_SharedState)
/* Descriptor heaps pool */
P_Mutex command_descriptor_heaps_mutex;
Arena *command_descriptor_heaps_arena;
struct command_descriptor_heap *first_submitted_command_descriptor_heap;
struct command_descriptor_heap *last_submitted_command_descriptor_heap;
GPU_D12_CommandDescriptorHeap *first_submitted_command_descriptor_heap;
GPU_D12_CommandDescriptorHeap *last_submitted_command_descriptor_heap;
/* Command buffers pool */
P_Mutex command_buffers_mutex;
@ -391,12 +372,12 @@ Struct(GPU_D12_SharedState)
/* Resources pool */
P_Mutex resources_mutex;
Arena *resources_arena;
struct dx12_resource *first_free_resource;
GPU_D12_Resource *first_free_resource;
/* Swapchains pool */
P_Mutex swapchains_mutex;
Arena *swapchains_arena;
struct swapchain *first_free_swapchain;
GPU_D12_Swapchain *first_free_swapchain;
/* Shader bytecode archive */
TAR_Archive dxc_archive;
@ -404,11 +385,11 @@ Struct(GPU_D12_SharedState)
/* Pipeline cache */
P_Mutex pipelines_mutex;
Arena *pipelines_arena;
struct pipeline *first_free_pipeline;
GPU_D12_Pipeline *first_free_pipeline;
Dict *pipeline_descs;
Dict *top_pipelines; /* Latest pipelines */
Dict *top_successful_pipelines; /* Latest pipelines that successfully compiled */
struct pipeline_scope *first_free_pipeline_scope;
GPU_D12_PipelineScope *first_free_pipeline_scope;
/* Fenced release queue */
P_Mutex fenced_releases_mutex;
@ -429,13 +410,13 @@ Struct(GPU_D12_SharedState)
u32 desc_counts[D3D12_DESCRIPTOR_HEAP_TYPE_NUM_TYPES];
/* Global descriptor heaps */
struct cpu_descriptor_heap *cbv_srv_uav_heap;
struct cpu_descriptor_heap *rtv_heap;
GPU_D12_CpuDescriptorHeap *cbv_srv_uav_heap;
GPU_D12_CpuDescriptorHeap *rtv_heap;
/* Command queues */
P_Mutex global_command_list_record_mutex;
P_Mutex global_submit_mutex;
struct command_queue *command_queues[DX12_NUM_QUEUES];
GPU_D12_CommandQueue *command_queues[DX12_NUM_QUEUES];
/* Evictor job */
P_Counter evictor_job_counter;
@ -493,20 +474,20 @@ P_JobDef(shader_compile_job, job);
P_JobDef(pipeline_alloc_job, job);
void pipeline_release_now(struct pipeline *pipeline);
void pipeline_release_now(GPU_D12_Pipeline *pipeline);
/* ========================== *
* Pipeline cache
* ========================== */
struct pipeline_scope *pipeline_scope_begin(void);
GPU_D12_PipelineScope *pipeline_scope_begin(void);
void pipeline_scope_end(struct pipeline_scope *scope);
void pipeline_scope_end(GPU_D12_PipelineScope *scope);
extern Readonly struct pipeline g_nil_pipeline;
struct pipeline *pipeline_from_name(struct pipeline_scope *scope, String name);
extern Readonly GPU_D12_Pipeline g_nil_pipeline;
GPU_D12_Pipeline *pipeline_from_name(GPU_D12_PipelineScope *scope, String name);
void pipeline_register(u64 num_pipelines, struct pipeline **pipelines);
void pipeline_register(u64 num_pipelines, GPU_D12_Pipeline **pipelines);
W_CallbackFuncDef(pipeline_watch_callback, name);
@ -514,29 +495,29 @@ W_CallbackFuncDef(pipeline_watch_callback, name);
* Descriptor
* ========================== */
struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh);
GPU_D12_Descriptor *descriptor_alloc(GPU_D12_CpuDescriptorHeap *dh);
void descriptor_release(struct descriptor *descriptor);
void descriptor_release(GPU_D12_Descriptor *descriptor);
/* ========================== *
* CPU descriptor heap
* ========================== */
struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
GPU_D12_CpuDescriptorHeap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
/* ========================== *
* Fenced release
* ========================== */
void fenced_release(void *data, enum fenced_release_kind kind);
void fenced_release(void *data, GPU_D12_FencedReleaseKind kind);
/* ========================== *
* Resource
* ========================== */
struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state);
GPU_D12_Resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state);
void dx12_resource_release_now(struct dx12_resource *t);
void dx12_resource_release_now(GPU_D12_Resource *t);
void GPU_ReleaseResource(GPU_Resource *resource);
@ -547,7 +528,7 @@ void GPU_ReleaseResource(GPU_Resource *resource);
struct dx12_resource_barrier_desc
{
enum D3D12_RESOURCE_BARRIER_TYPE type;
struct dx12_resource *resource;
GPU_D12_Resource *resource;
enum D3D12_RESOURCE_STATES new_state; /* 0 if type != D3D12_RESOURCE_BARRIER_TYPE_TRANSITION */
};
@ -559,24 +540,24 @@ void dx12_resource_barriers(ID3D12GraphicsCommandList *cl, i32 num_descs, struct
P_JobDef(command_queue_alloc_job, job);
void command_queue_release(struct command_queue *cq);
void command_queue_release(GPU_D12_CommandQueue *cq);
/* ========================== *
* Command list
* ========================== */
struct command_list_pool *command_list_pool_alloc(struct command_queue *cq);
GPU_D12_CommandListPool *command_list_pool_alloc(GPU_D12_CommandQueue *cq);
struct command_list *command_list_open(struct command_list_pool *pool);
GPU_D12_CommandList *command_list_open(GPU_D12_CommandListPool *pool);
/* TODO: Allow multiple command list submissions */
u64 command_list_close(struct command_list *cl);
u64 command_list_close(GPU_D12_CommandList *cl);
/* ========================== *
* Command descriptor heap (GPU / shader visible descriptor heap)
* ========================== */
struct command_descriptor_heap *command_list_push_descriptor_heap(struct command_list *cl, struct cpu_descriptor_heap *dh_cpu);
GPU_D12_CommandDescriptorHeap *command_list_push_descriptor_heap(GPU_D12_CommandList *cl, GPU_D12_CpuDescriptorHeap *dh_cpu);
/* ========================== *
* Command buffer
@ -587,7 +568,7 @@ u64 command_buffer_hash_from_size(u64 size);
u64 align_up_pow2(u64 v);
#define command_list_push_buffer(cl, count, elems) _command_list_push_buffer((cl), count * ((elems) ? sizeof(*(elems)) : 0), (elems), (elems) ? sizeof(*(elems)) : 1)
struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 data_len, void *data, u64 data_stride);
GPU_D12_CommandBuffer *_command_list_push_buffer(GPU_D12_CommandList *cl, u64 data_len, void *data, u64 data_stride);
/* ========================== *
* Wait job
@ -619,33 +600,33 @@ P_JobDef(dx12_upload_job, job);
* Run utils
* ========================== */
void command_list_set_pipeline(struct command_list *cl, struct pipeline *pipeline);
void command_list_set_pipeline(GPU_D12_CommandList *cl, GPU_D12_Pipeline *pipeline);
void command_list_set_sig(struct command_list *cl, void *src, u32 size);
void command_list_set_sig(GPU_D12_CommandList *cl, void *src, u32 size);
struct D3D12_VIEWPORT viewport_from_rect(Rect r);
D3D12_RECT scissor_from_rect(Rect r);
D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(struct command_buffer *cb, u32 vertex_size);
D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(GPU_D12_CommandBuffer *cb, u32 vertex_size);
D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(struct command_buffer *cb, DXGI_FORMAT format);
D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(GPU_D12_CommandBuffer *cb, DXGI_FORMAT format);
struct dx12_resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state);
GPU_D12_Resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state);
/* Calculate the view projection matrix */
Inline Mat4x4 calculate_vp(Xform view, f32 viewport_width, f32 viewport_height);
D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(struct descriptor *descriptor, struct command_descriptor_heap *cdh);
D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(GPU_D12_Descriptor *descriptor, GPU_D12_CommandDescriptorHeap *cdh);
/* ========================== *
* Render sig
* ========================== */
struct render_sig *render_sig_alloc(void);
GPU_D12_RenderSig *render_sig_alloc(void);
void render_sig_reset(struct render_sig *sig);
void render_sig_reset(GPU_D12_RenderSig *sig);
GPU_RenderSig *GPU_AllocRenderSig(void);
@ -667,7 +648,7 @@ GPU_MemoryInfo GPU_QueryMemoryInfo(void);
* Swapchain
* ========================== */
void swapchain_init_resources(struct swapchain *swapchain);
void swapchain_init_resources(GPU_D12_Swapchain *swapchain);
GPU_Swapchain *GPU_AllocSwapchain(P_Window *window, Vec2I32 resolution);
@ -675,13 +656,13 @@ void GPU_ReleaseSwapchain(GPU_Swapchain *gp_swapchain);
void GPU_WaitOnSwapchain(GPU_Swapchain *gp_swapchain);
struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 resolution);
GPU_D12_SwapchainBuffer *update_swapchain(GPU_D12_Swapchain *swapchain, Vec2I32 resolution);
/* ========================== *
* Present
* ========================== */
void present_blit(struct swapchain_buffer *dst, struct dx12_resource *src, Xform src_xf);
void present_blit(GPU_D12_SwapchainBuffer *dst, GPU_D12_Resource *src, Xform src_xf);
void GPU_PresentSwapchain(GPU_Swapchain *gp_swapchain, Vec2I32 backbuffer_resolution, GPU_Resource *texture, Xform texture_xf, i32 vsync);