From bdac09337853c9fcc789d77cce9acdcfd633ff83 Mon Sep 17 00:00:00 2001
From: jacob <jacob@cagori.com>
Date: Thu, 31 Jul 2025 22:00:24 -0500
Subject: [PATCH] gpu layer refactor progress

---
 src/gpu/gpu_dx12.c | 416 ++++++++++++++++++++++-----------------------
 src/gpu/gpu_dx12.h | 295 +++++++++++++++-----------------
 2 files changed, 346 insertions(+), 365 deletions(-)

diff --git a/src/gpu/gpu_dx12.c b/src/gpu/gpu_dx12.c
index 40fe3632..0904156e 100644
--- a/src/gpu/gpu_dx12.c
+++ b/src/gpu/gpu_dx12.c
@@ -83,7 +83,7 @@ P_ExitFuncDef(gp_shutdown)
     //IDXGISwapChain3_Release(g->swapchain);
     for (u32 i = 0; i < countof(g->command_queues); ++i)
     {
-        struct command_queue *cq = g->command_queues[i];
+        GPU_D12_CommandQueue *cq = g->command_queues[i];
         cmomand_queue_release(cq);
     }
     ID3D12Device_Release(g->device);
@@ -316,13 +316,13 @@ void dx12_init_objects(void)
     /* Create command queues */
     {
         __profn("Allocate command queues");
-        struct command_queue_desc params[] = {
+        GPU_D12_CommandQueueDesc params[] = {
             {.type = D3D12_COMMAND_LIST_TYPE_DIRECT, .priority = D3D12_COMMAND_QUEUE_PRIORITY_NORMAL, .dbg_name = Lit("Direct queue") },
             {.type = D3D12_COMMAND_LIST_TYPE_COMPUTE, .priority = D3D12_COMMAND_QUEUE_PRIORITY_NORMAL, .dbg_name = Lit("Compute queue") },
             {.type = D3D12_COMMAND_LIST_TYPE_COPY, .priority = D3D12_COMMAND_QUEUE_PRIORITY_HIGH, .dbg_name = Lit("Copyqueue") },
             {.type = D3D12_COMMAND_LIST_TYPE_COPY, .priority = D3D12_COMMAND_QUEUE_PRIORITY_NORMAL, .dbg_name = Lit("Background copy queue") }
         };
-        struct command_queue_alloc_job_sig sig = ZI;
+        GPU_D12_AllocCommandQueueJobSig sig = ZI;
         sig.descs_in = params;
         sig.cqs_out = g->command_queues;
         {
@@ -336,7 +336,7 @@ void dx12_init_objects(void)
             __profn("Initialize command queue profiling contexts");
             for (i32 i = 0; i < DX12_NUM_QUEUES; ++i)
             {
-                struct command_queue *cq = g->command_queues[i];
+                GPU_D12_CommandQueue *cq = g->command_queues[i];
                 String dbg_name = params[i].dbg_name;
                 __prof_dx12_ctx_alloc(cq->prof, g->device, cq->cq, dbg_name.text, dbg_name.len);
                 (UNUSED)dbg_name;
@@ -350,7 +350,7 @@ void dx12_init_objects(void)
  * Dx12 pipeline initialization
  * ========================== */
 
-void pipeline_register(u64 num_pipelines, struct pipeline **pipelines);
+void pipeline_register(u64 num_pipelines, GPU_D12_Pipeline **pipelines);
 
 void dx12_init_pipelines(void)
 {
@@ -362,7 +362,7 @@ void dx12_init_pipelines(void)
     {
         /* Material pipeline */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_material");
             desc->rtvs[0].format = DXGI_FORMAT_R8G8B8A8_UNORM;
             desc->rtvs[0].blending = 1;
@@ -372,19 +372,19 @@ void dx12_init_pipelines(void)
         }
         /* Flood pipeline */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_flood");
             SetDictValue(g->pipelines_arena, g->pipeline_descs, HashFnv64(Fnv64Basis, desc->name), (u64)desc);
         }
         /* Shade pipeline */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_shade");
             SetDictValue(g->pipelines_arena, g->pipeline_descs, HashFnv64(Fnv64Basis, desc->name), (u64)desc);
         }
         /* Shape pipeline */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_shape");
             desc->rtvs[0].format = DXGI_FORMAT_R8G8B8A8_UNORM;
             desc->rtvs[0].blending = 1;
@@ -392,7 +392,7 @@ void dx12_init_pipelines(void)
         }
         /* UI pipeline */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_ui");
             desc->rtvs[0].format = DXGI_FORMAT_R8G8B8A8_UNORM;
             desc->rtvs[0].blending = 1;
@@ -400,7 +400,7 @@ void dx12_init_pipelines(void)
         }
         /* Blit pipeilne */
         {
-            struct pipeline_desc *desc = PushStruct(g->pipelines_arena, struct pipeline_desc);
+            GPU_D12_PipelineDesc *desc = PushStruct(g->pipelines_arena, GPU_D12_PipelineDesc);
             desc->name = Lit("kernel_blit");
             desc->rtvs[0].format = DXGI_FORMAT_R8G8B8A8_UNORM;
             desc->rtvs[0].blending = 1;
@@ -410,17 +410,17 @@ void dx12_init_pipelines(void)
 
     /* Compile pipelines */
     u32 num_pipelines = 0;
-    struct pipeline_desc *descs = PushDry(scratch.arena, struct pipeline_desc);
+    GPU_D12_PipelineDesc *descs = PushDry(scratch.arena, GPU_D12_PipelineDesc);
     for (DictEntry *entry = g->pipeline_descs->first; entry; entry = entry->next)
     {
-        struct pipeline_desc *desc = (struct pipeline_desc *)entry->value;
-        *PushStruct(scratch.arena, struct pipeline_desc) = *desc;
+        GPU_D12_PipelineDesc *desc = (GPU_D12_PipelineDesc *)entry->value;
+        *PushStruct(scratch.arena, GPU_D12_PipelineDesc) = *desc;
         ++num_pipelines;
     }
-    struct pipeline **pipelines = PushStructs(scratch.arena, struct pipeline *, num_pipelines);
+    GPU_D12_Pipeline **pipelines = PushStructs(scratch.arena, GPU_D12_Pipeline *, num_pipelines);
     {
         __profn("Allocate pipelines");
-        struct pipeline_alloc_job_sig sig = ZI;
+        GPU_D12_AllocPipelineJobSig sig = ZI;
         sig.descs_in = descs;
         sig.pipelines_out = pipelines;
         P_Counter counter = ZI;
@@ -429,7 +429,7 @@ void dx12_init_pipelines(void)
     }
     for (u32 i = 0; i < num_pipelines; ++i)
     {
-        struct pipeline *pipeline = pipelines[i];
+        GPU_D12_Pipeline *pipeline = pipelines[i];
         if (pipeline->success)
         {
             P_LogSuccessF("Successfully compiled pipeline \"%F\" in %F seconds", FmtString(pipeline->name), FmtFloat(SecondsFromNs(pipeline->compilation_time_ns)));
@@ -497,14 +497,14 @@ void dx12_init_noise(void)
                 desc.SampleDesc.Count = 1;
                 desc.SampleDesc.Quality = 0;
 
-                struct dx12_resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, D3D12_RESOURCE_STATE_COPY_DEST);
+                GPU_D12_Resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, D3D12_RESOURCE_STATE_COPY_DEST);
                 r->srv_descriptor = descriptor_alloc(g->cbv_srv_uav_heap);
                 ID3D12Device_CreateShaderResourceView(g->device, r->resource, 0, r->srv_descriptor->handle);
 
                 /* Upload texture */
                 {
                     P_Counter counter = ZI;
-                    struct dx12_upload_job_sig sig = ZI;
+                    GPU_D12_UploadJobSig sig = ZI;
                     sig.resource = r;
                     sig.data = data.text;
                     P_Run(1, dx12_upload_job, &sig, P_Pool_Inherit, P_Priority_Inherit, &counter);
@@ -531,10 +531,10 @@ void dx12_init_noise(void)
 P_JobDef(shader_compile_job, job)
 {
     __prof;
-    struct shader_compile_job_sig *sig = job.sig;
+    GPU_D12_CompileShaderJobSig *sig = job.sig;
     Arena *arena = sig->arena;
-    struct shader_compile_desc *desc = &sig->descs[job.id];
-    struct shader_compile_result *result = &sig->results[job.id];
+    GPU_D12_ShaderDesc *desc = &sig->descs[job.id];
+    GPU_D12_CompiledShaderResult *result = &sig->results[job.id];
 
     TempArena scratch = BeginScratch(arena);
     {
@@ -583,11 +583,11 @@ P_JobDef(pipeline_alloc_job, job)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct pipeline_alloc_job_sig *sig = job.sig;
-    struct pipeline_desc *desc = &sig->descs_in[job.id];
-    struct pipeline **pipelines_out = sig->pipelines_out;
+    GPU_D12_AllocPipelineJobSig *sig = job.sig;
+    GPU_D12_PipelineDesc *desc = &sig->descs_in[job.id];
+    GPU_D12_Pipeline **pipelines_out = sig->pipelines_out;
 
-    struct pipeline *pipeline = 0;
+    GPU_D12_Pipeline *pipeline = 0;
     {
         P_Lock lock = P_LockE(&g->pipelines_mutex);
         if (g->first_free_pipeline)
@@ -597,7 +597,7 @@ P_JobDef(pipeline_alloc_job, job)
         }
         else
         {
-            pipeline = PushStructNoZero(g->pipelines_arena, struct pipeline);
+            pipeline = PushStructNoZero(g->pipelines_arena, GPU_D12_Pipeline);
         }
         P_Unlock(&lock);
     }
@@ -907,7 +907,7 @@ P_JobDef(pipeline_alloc_job, job)
     EndScratch(scratch);
 }
 
-void pipeline_release_now(struct pipeline *pipeline)
+void pipeline_release_now(GPU_D12_Pipeline *pipeline)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -927,11 +927,11 @@ void pipeline_release_now(struct pipeline *pipeline)
  * Pipeline cache
  * ========================== */
 
-struct pipeline_scope *pipeline_scope_begin(void)
+GPU_D12_PipelineScope *pipeline_scope_begin(void)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct pipeline_scope *scope = 0;
+    GPU_D12_PipelineScope *scope = 0;
     {
         P_Lock lock = P_LockE(&g->pipelines_mutex);
         if (g->first_free_pipeline_scope)
@@ -951,13 +951,13 @@ struct pipeline_scope *pipeline_scope_begin(void)
         arena = AllocArena(Mebi(64));
     }
     ResetArena(arena);
-    scope = PushStruct(arena, struct pipeline_scope);
+    scope = PushStruct(arena, GPU_D12_PipelineScope);
     scope->arena = arena;
     scope->refs = InitDict(scope->arena, 64);
     return scope;
 }
 
-void pipeline_scope_end(struct pipeline_scope *scope)
+void pipeline_scope_end(GPU_D12_PipelineScope *scope)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -965,10 +965,10 @@ void pipeline_scope_end(struct pipeline_scope *scope)
     {
         for (DictEntry *entry = scope->refs->first; entry; entry = entry->next)
         {
-            struct pipeline *pipeline = (struct pipeline *)entry->value;
+            GPU_D12_Pipeline *pipeline = (GPU_D12_Pipeline *)entry->value;
             if (--pipeline->refcount <= 0)
             {
-                fenced_release(pipeline, FENCED_RELEASE_KIND_PIPELINE);
+                fenced_release(pipeline, GPU_D12_FencedReleaseKind_Pipeline);
             }
         }
         scope->next_free = g->first_free_pipeline_scope;
@@ -977,15 +977,15 @@ void pipeline_scope_end(struct pipeline_scope *scope)
     P_Unlock(&lock);
 }
 
-Readonly struct pipeline g_nil_pipeline = ZI;
-struct pipeline *pipeline_from_name(struct pipeline_scope *scope, String name)
+Readonly GPU_D12_Pipeline g_nil_pipeline = ZI;
+GPU_D12_Pipeline *pipeline_from_name(GPU_D12_PipelineScope *scope, String name)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct pipeline *result = &g_nil_pipeline;
+    GPU_D12_Pipeline *result = &g_nil_pipeline;
     u64 hash = HashFnv64(Fnv64Basis, name);
 
-    struct pipeline *tmp = (struct pipeline *)DictValueFromHash(scope->refs, hash);
+    GPU_D12_Pipeline *tmp = (GPU_D12_Pipeline *)DictValueFromHash(scope->refs, hash);
     if (tmp)
     {
         result = tmp;
@@ -994,7 +994,7 @@ struct pipeline *pipeline_from_name(struct pipeline_scope *scope, String name)
     {
         {
             P_Lock lock = P_LockE(&g->pipelines_mutex);
-            tmp = (struct pipeline *)DictValueFromHash(g->top_successful_pipelines, hash);
+            tmp = (GPU_D12_Pipeline *)DictValueFromHash(g->top_successful_pipelines, hash);
             if (tmp)
             {
                 ++tmp->refcount;
@@ -1011,7 +1011,7 @@ struct pipeline *pipeline_from_name(struct pipeline_scope *scope, String name)
     return result;
 }
 
-void pipeline_register(u64 num_pipelines, struct pipeline **pipelines)
+void pipeline_register(u64 num_pipelines, GPU_D12_Pipeline **pipelines)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -1019,14 +1019,14 @@ void pipeline_register(u64 num_pipelines, struct pipeline **pipelines)
     {
         for (u64 i = 0; i < num_pipelines; ++i)
         {
-            struct pipeline *pipeline = pipelines[i];
+            GPU_D12_Pipeline *pipeline = pipelines[i];
             u64 hash = pipeline->hash;
             /* Insert into top dict */
             {
-                struct pipeline *old_pipeline = (struct pipeline *)DictValueFromHash(g->top_pipelines, hash);
+                GPU_D12_Pipeline *old_pipeline = (GPU_D12_Pipeline *)DictValueFromHash(g->top_pipelines, hash);
                 if (old_pipeline && --old_pipeline->refcount <= 0)
                 {
-                    fenced_release(old_pipeline, FENCED_RELEASE_KIND_PIPELINE);
+                    fenced_release(old_pipeline, GPU_D12_FencedReleaseKind_Pipeline);
                 }
                 SetDictValue(g->pipelines_arena, g->top_pipelines, hash, (u64)pipeline);
                 ++pipeline->refcount;
@@ -1034,10 +1034,10 @@ void pipeline_register(u64 num_pipelines, struct pipeline **pipelines)
             /* Insert into success dict */
             if (pipeline->success)
             {
-                struct pipeline *old_pipeline = (struct pipeline *)DictValueFromHash(g->top_successful_pipelines, hash);
+                GPU_D12_Pipeline *old_pipeline = (GPU_D12_Pipeline *)DictValueFromHash(g->top_successful_pipelines, hash);
                 if (old_pipeline && --old_pipeline->refcount <= 0)
                 {
-                    fenced_release(old_pipeline, FENCED_RELEASE_KIND_PIPELINE);
+                    fenced_release(old_pipeline, GPU_D12_FencedReleaseKind_Pipeline);
                 }
                 SetDictValue(g->pipelines_arena, g->top_successful_pipelines, hash, (u64)pipeline);
                 ++pipeline->refcount;
@@ -1066,8 +1066,8 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
     String pipeline_name = ZI;
     String friendly_name = ZI;
     i32 num_shaders = 0;
-    struct shader_compile_desc *shader_descs = 0;
-    struct shader_compile_result *shader_results = 0;
+    GPU_D12_ShaderDesc *shader_descs = 0;
+    GPU_D12_CompiledShaderResult *shader_results = 0;
     if (is_rs || is_cs)
     {
         P_LogDebugF("Change detected in shader source file \"%F\", recompiling...", FmtString(name));
@@ -1087,13 +1087,13 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
             pipeline_name = split.count > 1 ? split.strings[split.count - 2] : pipeline_name;
         }
         {
-            struct shader_compile_job_sig sig = ZI;
+            GPU_D12_CompileShaderJobSig sig = ZI;
             sig.arena = scratch.arena;
             if (is_rs)
             {
                 num_shaders = 2;
-                shader_descs = PushStructs(scratch.arena, struct shader_compile_desc, num_shaders);
-                shader_results = PushStructs(scratch.arena, struct shader_compile_result, num_shaders);
+                shader_descs = PushStructs(scratch.arena, GPU_D12_ShaderDesc, num_shaders);
+                shader_results = PushStructs(scratch.arena, GPU_D12_CompiledShaderResult, num_shaders);
                 sig.descs = shader_descs;
                 sig.results = shader_results;
                 sig.descs[0].src = data;
@@ -1108,8 +1108,8 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
             else if (is_cs)
             {
                 num_shaders = 1;
-                shader_descs = PushStructs(scratch.arena, struct shader_compile_desc, num_shaders);
-                shader_results = PushStructs(scratch.arena, struct shader_compile_result, num_shaders);
+                shader_descs = PushStructs(scratch.arena, GPU_D12_ShaderDesc, num_shaders);
+                shader_results = PushStructs(scratch.arena, GPU_D12_CompiledShaderResult, num_shaders);
                 sig.descs = shader_descs;
                 sig.results = shader_results;
                 sig.descs[0].src = data;
@@ -1129,8 +1129,8 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
 
     for (i32 i = 0; i < num_shaders; ++i)
     {
-        struct shader_compile_desc *desc = &shader_descs[i];
-        struct shader_compile_result *result = &shader_results[i];
+        GPU_D12_ShaderDesc *desc = &shader_descs[i];
+        GPU_D12_CompiledShaderResult *result = &shader_results[i];
         if (result->success)
         {
             P_LogSuccessF("Finished compiling shader \"%F:%F\" in %F seconds", FmtString(desc->friendly_name), FmtString(desc->entry), FmtFloat(SecondsFromNs(result->elapsed_ns)));
@@ -1152,11 +1152,11 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
     {
         /* Create pipeline descs */
         u32 num_pipelines = 0;
-        struct pipeline_desc *pipeline_descs = PushDry(scratch.arena, struct pipeline_desc);
+        GPU_D12_PipelineDesc *pipeline_descs = PushDry(scratch.arena, GPU_D12_PipelineDesc);
         for (DictEntry *entry = g->pipeline_descs->first; entry; entry = entry->next)
         {
-            struct pipeline_desc *pipeline_desc = (struct pipeline_desc *)entry->value;
-            struct pipeline_desc new_pipeline_desc = *pipeline_desc;
+            GPU_D12_PipelineDesc *pipeline_desc = (GPU_D12_PipelineDesc *)entry->value;
+            GPU_D12_PipelineDesc new_pipeline_desc = *pipeline_desc;
             if (EqString(pipeline_desc->name, pipeline_name))
             {
                 if (is_rs)
@@ -1168,7 +1168,7 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
                 {
                     new_pipeline_desc.cs_dxc = shader_results[0].dxc;
                 }
-                *PushStructNoZero(scratch.arena, struct pipeline_desc) = new_pipeline_desc;
+                *PushStructNoZero(scratch.arena, GPU_D12_PipelineDesc) = new_pipeline_desc;
                 ++num_pipelines;
             }
         }
@@ -1177,9 +1177,9 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
         if (num_pipelines > 0)
         {
             __profn("Compile dirty pipelines");
-            struct pipeline **pipelines = PushStructs(scratch.arena, struct pipeline *, num_pipelines);
+            GPU_D12_Pipeline **pipelines = PushStructs(scratch.arena, GPU_D12_Pipeline *, num_pipelines);
             {
-                struct pipeline_alloc_job_sig sig = ZI;
+                GPU_D12_AllocPipelineJobSig sig = ZI;
                 sig.descs_in = pipeline_descs;
                 sig.pipelines_out = pipelines;
                 P_Counter counter = ZI;
@@ -1190,7 +1190,7 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
                 P_Lock lock = P_LockS(&g->pipelines_mutex);
                 for (u32 i = 0; i < num_pipelines; ++i)
                 {
-                    struct pipeline *pipeline = pipelines[i];
+                    GPU_D12_Pipeline *pipeline = pipelines[i];
                     if (pipeline->success)
                     {
                         P_LogSuccessF("Successfully compiled pipeline \"%F\" in %F seconds", FmtString(pipeline->name), FmtFloat(SecondsFromNs(pipeline->compilation_time_ns)));
@@ -1207,7 +1207,7 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
                             String msg = StringFormat(scratch.arena, Lit("Error compiling pipeline \"%F\":\n%F"), FmtString(pipeline->name), FmtString(error));
                             P_LogError(msg);
                         }
-                        struct pipeline *old_pipeline = (struct pipeline *)DictValueFromHash(g->top_successful_pipelines, pipeline->hash);
+                        GPU_D12_Pipeline *old_pipeline = (GPU_D12_Pipeline *)DictValueFromHash(g->top_successful_pipelines, pipeline->hash);
                         if (!old_pipeline)
                         {
                             /* If no previously successful pipeline exists, then show a message box rather than logging since logs may not be visible to user */
@@ -1232,10 +1232,10 @@ W_CallbackFuncDef(pipeline_watch_callback, name)
  * Descriptor
  * ========================== */
 
-struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh)
+GPU_D12_Descriptor *descriptor_alloc(GPU_D12_CpuDescriptorHeap *dh)
 {
     __prof;
-    struct descriptor *d = 0;
+    GPU_D12_Descriptor *d = 0;
     u32 index = 0;
     D3D12_CPU_DESCRIPTOR_HANDLE handle = ZI;
     {
@@ -1253,7 +1253,7 @@ struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh)
             {
                 P_Panic(Lit("Max descriptors reached in heap"));
             }
-            d = PushStructNoZero(dh->arena, struct descriptor);
+            d = PushStructNoZero(dh->arena, GPU_D12_Descriptor);
             index = dh->num_descriptors_reserved++;
             handle.ptr = dh->handle.ptr + (index * dh->descriptor_size);
         }
@@ -1266,9 +1266,9 @@ struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh)
     return d;
 }
 
-void descriptor_release(struct descriptor *descriptor)
+void descriptor_release(GPU_D12_Descriptor *descriptor)
 {
-    struct cpu_descriptor_heap *dh = descriptor->heap;
+    GPU_D12_CpuDescriptorHeap *dh = descriptor->heap;
     P_Lock lock = P_LockE(&dh->mutex);
     {
         descriptor->next_free = dh->first_free_descriptor;
@@ -1281,14 +1281,14 @@ void descriptor_release(struct descriptor *descriptor)
  * CPU descriptor heap
  * ========================== */
 
-struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type)
+GPU_D12_CpuDescriptorHeap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct cpu_descriptor_heap *dh = 0;
+    GPU_D12_CpuDescriptorHeap *dh = 0;
     {
         Arena *arena = AllocArena(Mebi(64));
-        dh = PushStruct(arena, struct cpu_descriptor_heap);
+        dh = PushStruct(arena, GPU_D12_CpuDescriptorHeap);
         dh->arena = arena;
     }
 
@@ -1320,7 +1320,7 @@ struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP
 }
 
 #if 0
-void cpu_descriptor_heap_release(struct cpu_descriptor_heap *dh)
+void cpu_descriptor_heap_release(GPU_D12_CpuDescriptorHeap *dh)
 {
     /* TODO */
     (UNUSED)dh;
@@ -1331,10 +1331,10 @@ void cpu_descriptor_heap_release(struct cpu_descriptor_heap *dh)
  * Fenced release
  * ========================== */
 
-void fenced_release(void *data, enum fenced_release_kind kind)
+void fenced_release(void *data, GPU_D12_FencedReleaseKind kind)
 {
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct fenced_release_data fr = ZI;
+    GPU_D12_FencedReleaseData fr = ZI;
     fr.kind = kind;
     fr.ptr = data;
 
@@ -1343,7 +1343,7 @@ void fenced_release(void *data, enum fenced_release_kind kind)
     /* Read current fence target values from command queues */
     for (u32 i = 0; i < countof(g->command_queues); ++i)
     {
-        struct command_queue *cq = g->command_queues[i];
+        GPU_D12_CommandQueue *cq = g->command_queues[i];
         P_Lock lock = P_LockS(&cq->submit_fence_mutex);
         {
             fr_targets[i] = cq->submit_fence_target;
@@ -1355,7 +1355,7 @@ void fenced_release(void *data, enum fenced_release_kind kind)
     {
         P_Lock lock = P_LockE(&g->fenced_releases_mutex);
         {
-            *PushStruct(g->fenced_releases_arena, struct fenced_release_data) = fr;
+            *PushStruct(g->fenced_releases_arena, GPU_D12_FencedReleaseData) = fr;
             CopyBytes(g->fenced_release_targets, fr_targets, sizeof(fr_targets));
         }
         P_Unlock(&lock);
@@ -1376,11 +1376,11 @@ void fenced_release(void *data, enum fenced_release_kind kind)
  * Resource
  * ========================== */
 
-struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state)
+GPU_D12_Resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct dx12_resource *r = 0;
+    GPU_D12_Resource *r = 0;
     {
         P_Lock lock = P_LockE(&g->resources_mutex);
         if (g->first_free_resource)
@@ -1390,7 +1390,7 @@ struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D1
         }
         else
         {
-            r = PushStructNoZero(g->resources_arena, struct dx12_resource);
+            r = PushStructNoZero(g->resources_arena, GPU_D12_Resource);
         }
         P_Unlock(&lock);
     }
@@ -1415,7 +1415,7 @@ struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D1
     return r;
 }
 
-void dx12_resource_release_now(struct dx12_resource *t)
+void dx12_resource_release_now(GPU_D12_Resource *t)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -1451,8 +1451,8 @@ void dx12_resource_release_now(struct dx12_resource *t)
 
 void GPU_ReleaseResource(GPU_Resource *resource)
 {
-    struct dx12_resource *r = (struct dx12_resource *)resource;
-    fenced_release(r, FENCED_RELEASE_KIND_RESOURCE);
+    GPU_D12_Resource *r = (GPU_D12_Resource *)resource;
+    fenced_release(r, GPU_D12_FencedReleaseKind_Resource);
 }
 
 /* ========================== *
@@ -1469,7 +1469,7 @@ void dx12_resource_barriers(ID3D12GraphicsCommandList *cl, i32 num_descs, struct
     for (i32 i = 0; i < num_descs; ++i)
     {
         struct dx12_resource_barrier_desc *desc = &descs[i];
-        struct dx12_resource *resource = desc->resource;
+        GPU_D12_Resource *resource = desc->resource;
         enum D3D12_RESOURCE_BARRIER_TYPE type = desc->type;
         if (type == D3D12_RESOURCE_BARRIER_TYPE_TRANSITION)
         {
@@ -1515,19 +1515,19 @@ void dx12_resource_barriers(ID3D12GraphicsCommandList *cl, i32 num_descs, struct
  * Command queue
  * ========================== */
 
-struct command_list_pool *command_list_pool_alloc(struct command_queue *cq);
+GPU_D12_CommandListPool *command_list_pool_alloc(GPU_D12_CommandQueue *cq);
 
 P_JobDef(command_queue_alloc_job, job)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct command_queue_alloc_job_sig *sig = job.sig;
-    struct command_queue_desc *desc = &sig->descs_in[job.id];
+    GPU_D12_AllocCommandQueueJobSig *sig = job.sig;
+    GPU_D12_CommandQueueDesc *desc = &sig->descs_in[job.id];
     {
-        struct command_queue *cq = 0;
+        GPU_D12_CommandQueue *cq = 0;
         {
             Arena *arena = AllocArena(Gibi(64));
-            cq = PushStruct(arena, struct command_queue);
+            cq = PushStruct(arena, GPU_D12_CommandQueue);
             cq->arena = arena;
         }
         cq->desc = *desc;
@@ -1554,7 +1554,7 @@ P_JobDef(command_queue_alloc_job, job)
     }
 }
 
-void command_queue_release(struct command_queue *cq)
+void command_queue_release(GPU_D12_CommandQueue *cq)
 {
     __prof;
     /* TODO */
@@ -1566,32 +1566,32 @@ void command_queue_release(struct command_queue *cq)
  * Command list
  * ========================== */
 
-struct command_list_pool *command_list_pool_alloc(struct command_queue *cq)
+GPU_D12_CommandListPool *command_list_pool_alloc(GPU_D12_CommandQueue *cq)
 {
-    struct command_list_pool *pool = 0;
+    GPU_D12_CommandListPool *pool = 0;
     {
         Arena *arena = AllocArena(Gibi(64));
-        pool = PushStruct(arena, struct command_list_pool);
+        pool = PushStruct(arena, GPU_D12_CommandListPool);
         pool->arena = arena;
     }
     pool->cq = cq;
     return pool;
 }
 
-struct command_list *command_list_open(struct command_list_pool *pool)
+GPU_D12_CommandList *command_list_open(GPU_D12_CommandListPool *pool)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct command_queue *cq = pool->cq;
+    GPU_D12_CommandQueue *cq = pool->cq;
     u64 completed_fence_value = ID3D12Fence_GetCompletedValue(cq->submit_fence);
 
-    struct command_list *cl = 0;
+    GPU_D12_CommandList *cl = 0;
     struct ID3D12GraphicsCommandList *old_cl = 0;
     struct ID3D12CommandAllocator *old_ca = 0;
     {
         P_Lock lock = P_LockE(&pool->mutex);
         /* Find first command list ready for reuse */
-        for (struct command_list *tmp = pool->first_submitted_command_list; tmp; tmp = tmp->next_submitted)
+        for (GPU_D12_CommandList *tmp = pool->first_submitted_command_list; tmp; tmp = tmp->next_submitted)
         {
             if (completed_fence_value >= tmp->submitted_fence_target)
             {
@@ -1604,8 +1604,8 @@ struct command_list *command_list_open(struct command_list_pool *pool)
             /* Remove from submitted list */
             old_cl = cl->cl;
             old_ca = cl->ca;
-            struct command_list *prev = cl->prev_submitted;
-            struct command_list *next = cl->next_submitted;
+            GPU_D12_CommandList *prev = cl->prev_submitted;
+            GPU_D12_CommandList *next = cl->next_submitted;
             if (prev)
             {
                 prev->next_submitted = next;
@@ -1625,7 +1625,7 @@ struct command_list *command_list_open(struct command_list_pool *pool)
         }
         else
         {
-            cl = PushStructNoZero(pool->arena, struct command_list);
+            cl = PushStructNoZero(pool->arena, GPU_D12_CommandList);
         }
         P_Unlock(&lock);
     }
@@ -1678,12 +1678,12 @@ struct command_list *command_list_open(struct command_list_pool *pool)
 }
 
 /* TODO: Allow multiple command list submissions */
-u64 command_list_close(struct command_list *cl)
+u64 command_list_close(GPU_D12_CommandList *cl)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct command_queue *cq = cl->cq;
-    struct command_list_pool *pool = cl->pool;
+    GPU_D12_CommandQueue *cq = cl->cq;
+    GPU_D12_CommandListPool *pool = cl->pool;
 
     /* Close */
     {
@@ -1714,7 +1714,7 @@ u64 command_list_close(struct command_list *cl)
     /* Add descriptor heaps to submitted list */
     {
         P_Lock lock = P_LockE(&g->command_descriptor_heaps_mutex);
-        for (struct command_descriptor_heap *cdh = cl->first_command_descriptor_heap; cdh; cdh = cdh->next_in_command_list)
+        for (GPU_D12_CommandDescriptorHeap *cdh = cl->first_command_descriptor_heap; cdh; cdh = cdh->next_in_command_list)
         {
             cdh->submitted_cq = cq;
             cdh->submitted_fence_target = submit_fence_target;
@@ -1734,9 +1734,9 @@ u64 command_list_close(struct command_list *cl)
     /* Add command buffers to submitted list */
     {
         P_Lock lock = P_LockE(&g->command_buffers_mutex);
-        for (struct command_buffer *cb = cl->first_command_buffer; cb; cb = cb->next_in_command_list)
+        for (GPU_D12_CommandBuffer *cb = cl->first_command_buffer; cb; cb = cb->next_in_command_list)
         {
-            struct command_buffer_group *group = cb->group;
+            GPU_D12_CommandBufferGroup *group = cb->group;
             cb->submitted_cq = cq;
             cb->submitted_fence_target = submit_fence_target;
             if (group->last_submitted)
@@ -1776,21 +1776,21 @@ u64 command_list_close(struct command_list *cl)
  * Command descriptor heap (GPU / shader visible descriptor heap)
  * ========================== */
 
-struct command_descriptor_heap *command_list_push_descriptor_heap(struct command_list *cl, struct cpu_descriptor_heap *dh_cpu)
+GPU_D12_CommandDescriptorHeap *command_list_push_descriptor_heap(GPU_D12_CommandList *cl, GPU_D12_CpuDescriptorHeap *dh_cpu)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
     Assert(dh_cpu->type == D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);  /* Src heap must have expected type */
 
     /* Allocate GPU heap */
-    struct command_descriptor_heap *cdh = 0;
+    GPU_D12_CommandDescriptorHeap *cdh = 0;
     ID3D12DescriptorHeap *old_heap = 0;
     D3D12_CPU_DESCRIPTOR_HANDLE old_start_cpu_handle = ZI;
     D3D12_GPU_DESCRIPTOR_HANDLE old_start_gpu_handle = ZI;
     {
         P_Lock lock = P_LockE(&g->command_descriptor_heaps_mutex);
         /* Find first heap ready for reuse */
-        for (struct command_descriptor_heap *tmp = g->first_submitted_command_descriptor_heap; tmp; tmp = tmp->next_submitted)
+        for (GPU_D12_CommandDescriptorHeap *tmp = g->first_submitted_command_descriptor_heap; tmp; tmp = tmp->next_submitted)
         {
             /* TODO: Cache completed fence values */
             u64 completed_fence_value = ID3D12Fence_GetCompletedValue(tmp->submitted_cq->submit_fence);
@@ -1806,8 +1806,8 @@ struct command_descriptor_heap *command_list_push_descriptor_heap(struct command
             old_heap = cdh->heap;
             old_start_cpu_handle = cdh->start_cpu_handle;
             old_start_gpu_handle = cdh->start_gpu_handle;
-            struct command_descriptor_heap *prev = cdh->prev_submitted;
-            struct command_descriptor_heap *next = cdh->next_submitted;
+            GPU_D12_CommandDescriptorHeap *prev = cdh->prev_submitted;
+            GPU_D12_CommandDescriptorHeap *next = cdh->next_submitted;
             if (prev)
             {
                 prev->next_submitted = next;
@@ -1828,7 +1828,7 @@ struct command_descriptor_heap *command_list_push_descriptor_heap(struct command
         else
         {
             /* No available heap available for reuse, allocate new */
-            cdh = PushStructNoZero(g->command_descriptor_heaps_arena, struct command_descriptor_heap);
+            cdh = PushStructNoZero(g->command_descriptor_heaps_arena, GPU_D12_CommandDescriptorHeap);
         }
         P_Unlock(&lock);
     }
@@ -1897,7 +1897,7 @@ u64 align_up_pow2(u64 v)
 }
 
 #define command_list_push_buffer(cl, count, elems) _command_list_push_buffer((cl), count * ((elems) ? sizeof(*(elems)) : 0), (elems), (elems) ? sizeof(*(elems)) : 1)
-struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 data_len, void *data, u64 data_stride)
+GPU_D12_CommandBuffer *_command_list_push_buffer(GPU_D12_CommandList *cl, u64 data_len, void *data, u64 data_stride)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -1909,25 +1909,25 @@ struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 da
     u64 size = MaxU64(DX12_COMMAND_BUFFER_MIN_SIZE, align_up_pow2(data_len));
 
     /* Allocate buffer */
-    struct command_buffer_group *cb_group = 0;
-    struct command_buffer *cb = 0;
-    struct dx12_resource *r = 0;
+    GPU_D12_CommandBufferGroup *cb_group = 0;
+    GPU_D12_CommandBuffer *cb = 0;
+    GPU_D12_Resource *r = 0;
     {
         P_Lock lock = P_LockE(&g->command_buffers_mutex);
 
         {
             u64 group_hash = command_buffer_hash_from_size(size);
             DictEntry *cb_group_entry = EnsureDictEntry(g->command_buffers_arena, g->command_buffers_dict, group_hash);
-            cb_group = (struct command_buffer_group *)cb_group_entry->value;
+            cb_group = (GPU_D12_CommandBufferGroup *)cb_group_entry->value;
             if (!cb_group)
             {
                 /* Create group */
-                cb_group = PushStruct(g->command_buffers_arena, struct command_buffer_group);
+                cb_group = PushStruct(g->command_buffers_arena, GPU_D12_CommandBufferGroup);
                 cb_group_entry->value = (u64)cb_group;
             }
         }
         /* Find first command buffer ready for reuse */
-        for (struct command_buffer *tmp = cb_group->first_submitted; tmp; tmp = tmp->next_submitted)
+        for (GPU_D12_CommandBuffer *tmp = cb_group->first_submitted; tmp; tmp = tmp->next_submitted)
         {
             /* TODO: Cache completed fence values */
             u64 completed_fence_value = ID3D12Fence_GetCompletedValue(tmp->submitted_cq->submit_fence);
@@ -1941,8 +1941,8 @@ struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 da
         {
             /* Remove from submitted list */
             r = cb->resource;
-            struct command_buffer *prev = cb->prev_submitted;
-            struct command_buffer *next = cb->next_submitted;
+            GPU_D12_CommandBuffer *prev = cb->prev_submitted;
+            GPU_D12_CommandBuffer *next = cb->next_submitted;
             if (prev)
             {
                 prev->next_submitted = next;
@@ -1963,7 +1963,7 @@ struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 da
         else
         {
             /* Allocate new */
-            cb = PushStructNoZero(g->command_buffers_arena, struct command_buffer);
+            cb = PushStructNoZero(g->command_buffers_arena, GPU_D12_CommandBuffer);
         }
         P_Unlock(&lock);
     }
@@ -2101,7 +2101,7 @@ GPU_Resource *GPU_AllocTexture(GPU_TextureFormat format, u32 flags, Vec2I32 size
 
     D3D12_RESOURCE_STATES initial_state = D3D12_RESOURCE_STATE_COPY_DEST;
 
-    struct dx12_resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, initial_state);
+    GPU_D12_Resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, initial_state);
     r->texture_size = size;
     r->srv_descriptor = descriptor_alloc(g->cbv_srv_uav_heap);
     ID3D12Device_CreateShaderResourceView(g->device, r->resource, 0, r->srv_descriptor->handle);
@@ -2119,7 +2119,7 @@ GPU_Resource *GPU_AllocTexture(GPU_TextureFormat format, u32 flags, Vec2I32 size
     {
         /* TODO: Make wait optional */
         P_Counter counter = ZI;
-        struct dx12_upload_job_sig sig = ZI;
+        GPU_D12_UploadJobSig sig = ZI;
         sig.resource = r;
         sig.data = initial_data;
         P_Run(1, dx12_upload_job, &sig, P_Pool_Inherit, P_Priority_Inherit, &counter);
@@ -2131,7 +2131,7 @@ GPU_Resource *GPU_AllocTexture(GPU_TextureFormat format, u32 flags, Vec2I32 size
 
 Vec2I32 GPU_GetTextureSize(GPU_Resource *resource)
 {
-    struct dx12_resource *r = (struct dx12_resource *)resource;
+    GPU_D12_Resource *r = (GPU_D12_Resource *)resource;
     return r->texture_size;
 }
 
@@ -2142,8 +2142,8 @@ Vec2I32 GPU_GetTextureSize(GPU_Resource *resource)
 P_JobDef(dx12_upload_job, job)
 {
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct dx12_upload_job_sig *sig = job.sig;
-    struct dx12_resource *r = sig->resource;
+    GPU_D12_UploadJobSig *sig = job.sig;
+    GPU_D12_Resource *r = sig->resource;
     void *data = sig->data;
 
     Assert(r->state == D3D12_RESOURCE_STATE_COPY_DEST);
@@ -2160,7 +2160,7 @@ P_JobDef(dx12_upload_job, job)
         D3D12_SUBRESOURCE_FOOTPRINT footprint = placed_footprint.Footprint;
 
         /* Create upload heap */
-        struct dx12_resource *upload = 0;
+        GPU_D12_Resource *upload = 0;
         {
             D3D12_HEAP_PROPERTIES upload_heap_props = { .Type = D3D12_HEAP_TYPE_UPLOAD };
             upload_heap_props.CPUPageProperty = D3D12_CPU_PAGE_PROPERTY_UNKNOWN;
@@ -2184,8 +2184,8 @@ P_JobDef(dx12_upload_job, job)
             upload = dx12_resource_alloc(upload_heap_props, upload_heap_flags, upload_desc, upload_initial_state);
         }
 
-        struct command_queue *cq = g->command_queues[DX12_QUEUE_COPY_BACKGROUND];
-        struct command_list *cl = command_list_open(cq->cl_pool);
+        GPU_D12_CommandQueue *cq = g->command_queues[DX12_QUEUE_COPY_BACKGROUND];
+        GPU_D12_CommandList *cl = command_list_open(cq->cl_pool);
         {
             /* Copyto upload heap */
             {
@@ -2252,7 +2252,7 @@ P_JobDef(dx12_upload_job, job)
  * Run utils
  * ========================== */
 
-void command_list_set_pipeline(struct command_list *cl, struct pipeline *pipeline)
+void command_list_set_pipeline(GPU_D12_CommandList *cl, GPU_D12_Pipeline *pipeline)
 {
     ID3D12GraphicsCommandList_SetPipelineState(cl->cl, pipeline->pso);
     if (pipeline->is_gfx)
@@ -2266,7 +2266,7 @@ void command_list_set_pipeline(struct command_list *cl, struct pipeline *pipelin
     cl->cur_pipeline = pipeline;
 }
 
-void command_list_set_sig(struct command_list *cl, void *src, u32 size)
+void command_list_set_sig(GPU_D12_CommandList *cl, void *src, u32 size)
 {
     __prof;
     Assert(size % 16 == 0);  /* Root constant structs must pad to 16 bytes */
@@ -2310,7 +2310,7 @@ D3D12_RECT scissor_from_rect(Rect r)
     return scissor;
 }
 
-D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(struct command_buffer *cb, u32 vertex_size)
+D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(GPU_D12_CommandBuffer *cb, u32 vertex_size)
 {
     D3D12_VERTEX_BUFFER_VIEW vbv = ZI;
     vbv.BufferLocation = cb->resource->gpu_address;
@@ -2319,7 +2319,7 @@ D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(struct command_buffer *cb, u32
     return vbv;
 }
 
-D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(struct command_buffer *cb, DXGI_FORMAT format)
+D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(GPU_D12_CommandBuffer *cb, DXGI_FORMAT format)
 {
     D3D12_INDEX_BUFFER_VIEW ibv = ZI;
     ibv.BufferLocation = cb->resource->gpu_address;
@@ -2328,7 +2328,7 @@ D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(struct command_buffer *cb, DXGI_
     return ibv;
 }
 
-struct dx12_resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state)
+GPU_D12_Resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -2351,7 +2351,7 @@ struct dx12_resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOUR
     desc.SampleDesc.Quality = 0;
     desc.Flags = D3D12_RESOURCE_FLAG_ALLOW_RENDER_TARGET | D3D12_RESOURCE_FLAG_ALLOW_UNORDERED_ACCESS;
 
-    struct dx12_resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, initial_state);
+    GPU_D12_Resource *r = dx12_resource_alloc(heap_props, heap_flags, desc, initial_state);
     r->srv_descriptor = descriptor_alloc(g->cbv_srv_uav_heap);
     r->uav_descriptor = descriptor_alloc(g->cbv_srv_uav_heap);
     r->rtv_descriptor = descriptor_alloc(g->rtv_heap);
@@ -2371,7 +2371,7 @@ Inline Mat4x4 calculate_vp(Xform view, f32 viewport_width, f32 viewport_height)
     return MulMat4x4(projection, view4x4);
 }
 
-D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(struct descriptor *descriptor, struct command_descriptor_heap *cdh)
+D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(GPU_D12_Descriptor *descriptor, GPU_D12_CommandDescriptorHeap *cdh)
 {
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
     struct D3D12_GPU_DESCRIPTOR_HANDLE result = ZI;
@@ -2383,13 +2383,13 @@ D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(struct descriptor *descri
  * Render sig
  * ========================== */
 
-struct render_sig *render_sig_alloc(void)
+GPU_D12_RenderSig *render_sig_alloc(void)
 {
     __prof;
-    struct render_sig *sig = 0;
+    GPU_D12_RenderSig *sig = 0;
     {
         Arena *arena = AllocArena(Mebi(64));
-        sig = PushStruct(arena, struct render_sig);
+        sig = PushStruct(arena, GPU_D12_RenderSig);
         sig->arena = arena;
     }
 
@@ -2402,7 +2402,7 @@ struct render_sig *render_sig_alloc(void)
     return sig;
 }
 
-void render_sig_reset(struct render_sig *sig)
+void render_sig_reset(GPU_D12_RenderSig *sig)
 {
     __prof;
 
@@ -2426,14 +2426,14 @@ void render_sig_reset(struct render_sig *sig)
 GPU_RenderSig *GPU_AllocRenderSig(void)
 {
     __prof;
-    struct render_sig *sig = render_sig_alloc();
+    GPU_D12_RenderSig *sig = render_sig_alloc();
     return (GPU_RenderSig *)sig;
 }
 
 u32 GPU_PushRenderCmd(GPU_RenderSig *render_sig, GPU_RenderCmdDesc *cmd_desc)
 {
     u32 ret = 0;
-    struct render_sig *sig = (struct render_sig *)render_sig;
+    GPU_D12_RenderSig *sig = (GPU_D12_RenderSig *)render_sig;
     if (sig)
     {
         switch (cmd_desc->kind)
@@ -2442,8 +2442,8 @@ u32 GPU_PushRenderCmd(GPU_RenderSig *render_sig, GPU_RenderCmdDesc *cmd_desc)
 
             case GP_RENDER_CMD_KIND_DRAW_MATERIAL:
             {
-                struct dx12_resource *texture = (struct dx12_resource *)cmd_desc->material.texture;
-                struct material_instance_desc *instance_desc = PushStruct(sig->material_instance_descs_arena, struct material_instance_desc);
+                GPU_D12_Resource *texture = (GPU_D12_Resource *)cmd_desc->material.texture;
+                GPU_D12_MaterialInstanceDesc *instance_desc = PushStruct(sig->material_instance_descs_arena, GPU_D12_MaterialInstanceDesc);
                 instance_desc->xf = cmd_desc->material.xf;
                 instance_desc->texture_id = texture ? texture->srv_descriptor->index : 0xFFFFFFFF;
                 instance_desc->clip = cmd_desc->material.clip;
@@ -2456,8 +2456,8 @@ u32 GPU_PushRenderCmd(GPU_RenderSig *render_sig, GPU_RenderCmdDesc *cmd_desc)
 
             case GP_RENDER_CMD_KIND_DRAW_UI_RECT:
             {
-                struct dx12_resource *texture = (struct dx12_resource *)cmd_desc->ui_rect.texture;
-                struct ui_rect_instance_desc *instance_desc = PushStruct(sig->ui_rect_instance_descs_arena, struct ui_rect_instance_desc);
+                GPU_D12_Resource *texture = (GPU_D12_Resource *)cmd_desc->ui_rect.texture;
+                GPU_D12_UiRectInstanceDesc *instance_desc = PushStruct(sig->ui_rect_instance_descs_arena, GPU_D12_UiRectInstanceDesc);
                 instance_desc->xf = cmd_desc->ui_rect.xf;
                 instance_desc->texture_id = texture ? texture->srv_descriptor->index : 0xFFFFFFFF;
                 instance_desc->clip = cmd_desc->ui_rect.clip;
@@ -2485,7 +2485,7 @@ u32 GPU_PushRenderCmd(GPU_RenderSig *render_sig, GPU_RenderCmdDesc *cmd_desc)
 
             case GP_RENDER_CMD_KIND_PUSH_GRID:
             {
-                struct material_grid_desc *grid_desc = PushStruct(sig->material_grid_descs_arena, struct material_grid_desc);
+                GPU_D12_MaterialGridDesc *grid_desc = PushStruct(sig->material_grid_descs_arena, GPU_D12_MaterialGridDesc);
                 grid_desc->line_thickness = cmd_desc->grid.line_thickness;
                 grid_desc->line_spacing = cmd_desc->grid.line_spacing;
                 grid_desc->offset = cmd_desc->grid.offset;
@@ -2510,7 +2510,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
     TempArena scratch = BeginScratchNoConflict();
-    struct render_sig *rsig = (struct render_sig *)gp_render_sig;
+    GPU_D12_RenderSig *rsig = (GPU_D12_RenderSig *)gp_render_sig;
     ++rsig->frame_index;
 
     Vec2I32 ui_size = VEC2I32(MaxI32(params.ui_size.x, 1), MaxI32(params.ui_size.y, 1));
@@ -2526,12 +2526,12 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
     if (rsig->shade_target && !EqVec2I32(render_size, rsig->shade_target->texture_size))
     {
         __profn("Release sig resources");
-        fenced_release(rsig->albedo, FENCED_RELEASE_KIND_RESOURCE);
-        fenced_release(rsig->emittance, FENCED_RELEASE_KIND_RESOURCE);
-        fenced_release(rsig->emittance_flood_read, FENCED_RELEASE_KIND_RESOURCE);
-        fenced_release(rsig->emittance_flood_target, FENCED_RELEASE_KIND_RESOURCE);
-        fenced_release(rsig->shade_read, FENCED_RELEASE_KIND_RESOURCE);
-        fenced_release(rsig->shade_target, FENCED_RELEASE_KIND_RESOURCE);
+        fenced_release(rsig->albedo, GPU_D12_FencedReleaseKind_Resource);
+        fenced_release(rsig->emittance, GPU_D12_FencedReleaseKind_Resource);
+        fenced_release(rsig->emittance_flood_read, GPU_D12_FencedReleaseKind_Resource);
+        fenced_release(rsig->emittance_flood_target, GPU_D12_FencedReleaseKind_Resource);
+        fenced_release(rsig->shade_read, GPU_D12_FencedReleaseKind_Resource);
+        fenced_release(rsig->shade_target, GPU_D12_FencedReleaseKind_Resource);
         rsig->shade_target = 0;
     }
     if (!rsig->shade_target)
@@ -2548,7 +2548,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
     /* Allocate ui buffers */
     if (rsig->ui_target && !EqVec2I32(ui_size, rsig->ui_target->texture_size))
     {
-        fenced_release(rsig->ui_target, FENCED_RELEASE_KIND_RESOURCE);
+        fenced_release(rsig->ui_target, GPU_D12_FencedReleaseKind_Resource);
         rsig->ui_target = 0;
     }
     if (!rsig->ui_target)
@@ -2556,15 +2556,15 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
         rsig->ui_target = gbuff_alloc(DXGI_FORMAT_R8G8B8A8_UNORM, ui_size, D3D12_RESOURCE_STATE_RENDER_TARGET);
     }
 
-    struct pipeline_scope *pipeline_scope = pipeline_scope_begin();
-    struct pipeline *material_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_material"));
-    struct pipeline *flood_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_flood"));
-    struct pipeline *shade_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_shade"));
-    struct pipeline *blit_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_blit"));
-    struct pipeline *ui_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_ui"));
-    struct pipeline *shape_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_shape"));
-    struct command_queue *cq = g->command_queues[DX12_QUEUE_DIRECT];
-    struct command_list *cl = command_list_open(cq->cl_pool);
+    GPU_D12_PipelineScope *pipeline_scope = pipeline_scope_begin();
+    GPU_D12_Pipeline *material_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_material"));
+    GPU_D12_Pipeline *flood_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_flood"));
+    GPU_D12_Pipeline *shade_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_shade"));
+    GPU_D12_Pipeline *blit_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_blit"));
+    GPU_D12_Pipeline *ui_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_ui"));
+    GPU_D12_Pipeline *shape_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_shape"));
+    GPU_D12_CommandQueue *cq = g->command_queues[DX12_QUEUE_DIRECT];
+    GPU_D12_CommandList *cl = command_list_open(cq->cl_pool);
     {
         __profn("Run render");
         __profnc_dx12(cl->cq->prof, cl->cl, "Run render", Rgb32F(0.5, 0.2, 0.2));
@@ -2582,8 +2582,8 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
         /* TODO: Make these static */
         /* Dummy vertex buffer */
         LocalPersist u16 quad_indices[6] = { 0, 1, 2, 0, 2, 3 };
-        struct command_buffer *dummy_vertex_buffer = command_list_push_buffer(cl, 0, (u8 *)0);
-        struct command_buffer *quad_index_buffer = command_list_push_buffer(cl, countof(quad_indices), quad_indices);
+        GPU_D12_CommandBuffer *dummy_vertex_buffer = command_list_push_buffer(cl, 0, (u8 *)0);
+        GPU_D12_CommandBuffer *quad_index_buffer = command_list_push_buffer(cl, countof(quad_indices), quad_indices);
 
         /* Process sig data into uploadable data */
         K_MaterialInstance *material_instances = PushStructsNoZero(scratch.arena, K_MaterialInstance, rsig->num_material_instance_descs);
@@ -2597,7 +2597,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
                 __profn("Process material instances");
                 for (u32 i = 0; i < rsig->num_material_instance_descs; ++i)
                 {
-                    struct material_instance_desc *desc = &((struct material_instance_desc *)ArenaBase(rsig->material_instance_descs_arena))[i];
+                    GPU_D12_MaterialInstanceDesc *desc = &((GPU_D12_MaterialInstanceDesc *)ArenaBase(rsig->material_instance_descs_arena))[i];
                     K_MaterialInstance *instance = &material_instances[i];
                     instance->tex_nurid = desc->texture_id;
                     instance->grid_id = desc->grid_id;
@@ -2615,7 +2615,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
                 __profn("Process ui rect instances");
                 for (u32 i = 0; i < rsig->num_ui_rect_instance_descs; ++i)
                 {
-                    struct ui_rect_instance_desc *desc = &((struct ui_rect_instance_desc *)ArenaBase(rsig->ui_rect_instance_descs_arena))[i];
+                    GPU_D12_UiRectInstanceDesc *desc = &((GPU_D12_UiRectInstanceDesc *)ArenaBase(rsig->ui_rect_instance_descs_arena))[i];
                     K_UiInstance *instance = &ui_rect_instances[i];
                     instance->tex_nurid = desc->texture_id;
                     instance->xf = desc->xf;
@@ -2630,7 +2630,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
                 __profn("Process grids");
                 for (u32 i = 0; i < rsig->num_material_grid_descs; ++i)
                 {
-                    struct material_grid_desc *desc = &((struct material_grid_desc *)ArenaBase(rsig->material_grid_descs_arena))[i];
+                    GPU_D12_MaterialGridDesc *desc = &((GPU_D12_MaterialGridDesc *)ArenaBase(rsig->material_grid_descs_arena))[i];
                     K_MaterialGrid *grid = &grids[i];
                     grid->line_thickness = desc->line_thickness;
                     grid->line_spacing = desc->line_spacing;
@@ -2647,14 +2647,14 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
         /* Upload buffers */
         u64 num_ui_shape_verts = rsig->ui_shape_verts_arena->pos / sizeof(K_ShapeVert);
         u64 num_ui_shape_indices = rsig->ui_shape_indices_arena->pos / sizeof(u32);
-        struct command_buffer *material_instance_buffer = command_list_push_buffer(cl, rsig->num_material_instance_descs, material_instances);
-        struct command_buffer *ui_rect_instance_buffer = command_list_push_buffer(cl, rsig->num_ui_rect_instance_descs, ui_rect_instances);
-        struct command_buffer *ui_shape_verts_buffer = command_list_push_buffer(cl, num_ui_shape_verts, (K_ShapeVert *)ArenaBase(rsig->ui_shape_verts_arena));
-        struct command_buffer *ui_shape_indices_buffer = command_list_push_buffer(cl, num_ui_shape_indices, (u32 *)ArenaBase(rsig->ui_shape_indices_arena));
-        struct command_buffer *grid_buffer = command_list_push_buffer(cl, rsig->num_material_grid_descs, grids);
+        GPU_D12_CommandBuffer *material_instance_buffer = command_list_push_buffer(cl, rsig->num_material_instance_descs, material_instances);
+        GPU_D12_CommandBuffer *ui_rect_instance_buffer = command_list_push_buffer(cl, rsig->num_ui_rect_instance_descs, ui_rect_instances);
+        GPU_D12_CommandBuffer *ui_shape_verts_buffer = command_list_push_buffer(cl, num_ui_shape_verts, (K_ShapeVert *)ArenaBase(rsig->ui_shape_verts_arena));
+        GPU_D12_CommandBuffer *ui_shape_indices_buffer = command_list_push_buffer(cl, num_ui_shape_indices, (u32 *)ArenaBase(rsig->ui_shape_indices_arena));
+        GPU_D12_CommandBuffer *grid_buffer = command_list_push_buffer(cl, rsig->num_material_grid_descs, grids);
 
         /* Upload descriptor heap */
-        struct command_descriptor_heap *descriptor_heap = command_list_push_descriptor_heap(cl, g->cbv_srv_uav_heap);
+        GPU_D12_CommandDescriptorHeap *descriptor_heap = command_list_push_descriptor_heap(cl, g->cbv_srv_uav_heap);
         ID3D12DescriptorHeap *heaps[] = { descriptor_heap->heap };
         ID3D12GraphicsCommandList_SetDescriptorHeaps(cl->cl, countof(heaps), heaps);
 
@@ -2772,7 +2772,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
                 ID3D12GraphicsCommandList_Dispatch(cl->cl, (render_size.x + 7) / 8, (render_size.y + 7) / 8, 1);
 
                 /* Swap buffers */
-                struct dx12_resource *swp = rsig->emittance_flood_read;
+                GPU_D12_Resource *swp = rsig->emittance_flood_read;
                 rsig->emittance_flood_read = rsig->emittance_flood_target;
                 rsig->emittance_flood_target = swp;
 
@@ -2853,7 +2853,7 @@ GPU_Resource *GPU_RunRender(GPU_RenderSig *gp_render_sig, GPU_RenderParams param
             ID3D12GraphicsCommandList_Dispatch(cl->cl, (render_size.x + 7) / 8, (render_size.y + 7) / 8, 1);
 
             /* Swap */
-            struct dx12_resource *swp = rsig->shade_read;
+            GPU_D12_Resource *swp = rsig->shade_read;
             rsig->shade_read = rsig->shade_target;
             rsig->shade_target = swp;
         }
@@ -3023,7 +3023,7 @@ GPU_MemoryInfo GPU_QueryMemoryInfo(void)
  * Swapchain
  * ========================== */
 
-void swapchain_init_resources(struct swapchain *swapchain)
+void swapchain_init_resources(GPU_D12_Swapchain *swapchain)
 {
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
     for (u32 i = 0; i < countof(swapchain->buffers); ++i)
@@ -3035,7 +3035,7 @@ void swapchain_init_resources(struct swapchain *swapchain)
             /* TODO: Don't panic */
             P_Panic(Lit("Failed to get swapchain buffer"));
         }
-        struct swapchain_buffer *sb = &swapchain->buffers[i];
+        GPU_D12_SwapchainBuffer *sb = &swapchain->buffers[i];
         ZeroStruct(sb);
         sb->swapchain = swapchain;
         sb->resource = resource;
@@ -3050,9 +3050,9 @@ GPU_Swapchain *GPU_AllocSwapchain(P_Window *window, Vec2I32 resolution)
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
     HRESULT hr = 0;
     HWND hwnd = (HWND)P_GetInternalWindowHandle(window);
-    struct command_queue *cq = g->command_queues[DX12_QUEUE_DIRECT];
+    GPU_D12_CommandQueue *cq = g->command_queues[DX12_QUEUE_DIRECT];
 
-    struct swapchain *swapchain = 0;
+    GPU_D12_Swapchain *swapchain = 0;
     {
         P_Lock lock = P_LockE(&g->swapchains_mutex);
         if (g->first_free_swapchain)
@@ -3062,7 +3062,7 @@ GPU_Swapchain *GPU_AllocSwapchain(P_Window *window, Vec2I32 resolution)
         }
         else
         {
-            swapchain = PushStruct(g->swapchains_arena, struct swapchain);
+            swapchain = PushStruct(g->swapchains_arena, GPU_D12_Swapchain);
         }
         P_Unlock(&lock);
     }
@@ -3123,7 +3123,7 @@ void GPU_ReleaseSwapchain(GPU_Swapchain *gp_swapchain)
 void GPU_WaitOnSwapchain(GPU_Swapchain *gp_swapchain)
 {
 #if DX12_WAIT_FRAME_LATENCY > 0
-    struct swapchain *swapchain = (struct swapchain *)gp_swapchain;
+    GPU_D12_Swapchain *swapchain = (GPU_D12_Swapchain *)gp_swapchain;
     if (swapchain->waitable)
     {
         WaitForSingleObjectEx(swapchain->waitable, 1000, 1);
@@ -3133,7 +3133,7 @@ void GPU_WaitOnSwapchain(GPU_Swapchain *gp_swapchain)
 #endif
 }
 
-struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 resolution)
+GPU_D12_SwapchainBuffer *update_swapchain(GPU_D12_Swapchain *swapchain, Vec2I32 resolution)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
@@ -3143,7 +3143,7 @@ struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 r
     if (should_rebuild)
     {
         HRESULT hr = 0;
-        struct command_queue *cq = g->command_queues[DX12_QUEUE_DIRECT];
+        GPU_D12_CommandQueue *cq = g->command_queues[DX12_QUEUE_DIRECT];
         /* Lock direct queue submissions (in case any write to backbuffer) */
         /* TODO: Less overkill approach - Only flush present_blit since we know it's the only operation targeting backbuffer */
         P_Lock lock = P_LockE(&cq->submit_fence_mutex);
@@ -3162,7 +3162,7 @@ struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 r
             /* Release buffers */
             for (u32 i = 0; i < countof(swapchain->buffers); ++i)
             {
-                struct swapchain_buffer *sb = &swapchain->buffers[i];
+                GPU_D12_SwapchainBuffer *sb = &swapchain->buffers[i];
                 descriptor_release(sb->rtv_descriptor);
                 ID3D12Resource_Release(sb->resource);
             }
@@ -3190,30 +3190,30 @@ struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 r
  * Present
  * ========================== */
 
-void present_blit(struct swapchain_buffer *dst, struct dx12_resource *src, Xform src_xf)
+void present_blit(GPU_D12_SwapchainBuffer *dst, GPU_D12_Resource *src, Xform src_xf)
 {
     __prof;
     GPU_D12_SharedState *g = &GPU_D12_shared_state;
-    struct pipeline_scope *pipeline_scope = pipeline_scope_begin();
-    struct pipeline *blit_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_blit"));
+    GPU_D12_PipelineScope *pipeline_scope = pipeline_scope_begin();
+    GPU_D12_Pipeline *blit_pipeline = pipeline_from_name(pipeline_scope, Lit("kernel_blit"));
     if (blit_pipeline->success)
     {
-        struct command_queue *cq = g->command_queues[DX12_QUEUE_DIRECT];
-        struct command_list *cl = command_list_open(cq->cl_pool);
+        GPU_D12_CommandQueue *cq = g->command_queues[DX12_QUEUE_DIRECT];
+        GPU_D12_CommandList *cl = command_list_open(cq->cl_pool);
         {
             __profn("Present blit");
             __profnc_dx12(cl->cq->prof, cl->cl, "Present blit", Rgb32F(0.5, 0.2, 0.2));
-            struct swapchain *swapchain = dst->swapchain;
+            GPU_D12_Swapchain *swapchain = dst->swapchain;
 
             /* Upload dummmy vert & index buffer */
             /* TODO: Make these static */
             /* Dummy vertex buffer */
             LocalPersist u16 quad_indices[6] = { 0, 1, 2, 0, 2, 3 };
-            struct command_buffer *dummy_vertex_buffer = command_list_push_buffer(cl, 0, (u8 *)0);
-            struct command_buffer *quad_index_buffer = command_list_push_buffer(cl, countof(quad_indices), quad_indices);
+            GPU_D12_CommandBuffer *dummy_vertex_buffer = command_list_push_buffer(cl, 0, (u8 *)0);
+            GPU_D12_CommandBuffer *quad_index_buffer = command_list_push_buffer(cl, countof(quad_indices), quad_indices);
 
             /* Upload descriptor heap */
-            struct command_descriptor_heap *descriptor_heap = command_list_push_descriptor_heap(cl, g->cbv_srv_uav_heap);
+            GPU_D12_CommandDescriptorHeap *descriptor_heap = command_list_push_descriptor_heap(cl, g->cbv_srv_uav_heap);
             ID3D12DescriptorHeap *heaps[] = { descriptor_heap->heap };
             ID3D12GraphicsCommandList_SetDescriptorHeaps(cl->cl, countof(heaps), heaps);
 
@@ -3294,9 +3294,9 @@ void present_blit(struct swapchain_buffer *dst, struct dx12_resource *src, Xform
 void GPU_PresentSwapchain(GPU_Swapchain *gp_swapchain, Vec2I32 backbuffer_resolution, GPU_Resource *texture, Xform texture_xf, i32 vsync)
 {
     __prof;
-    struct swapchain *swapchain = (struct swapchain *)gp_swapchain;
-    struct swapchain_buffer *swapchain_buffer = update_swapchain(swapchain, backbuffer_resolution);
-    struct dx12_resource *texture_resource = (struct dx12_resource *)texture;
+    GPU_D12_Swapchain *swapchain = (GPU_D12_Swapchain *)gp_swapchain;
+    GPU_D12_SwapchainBuffer *swapchain_buffer = update_swapchain(swapchain, backbuffer_resolution);
+    GPU_D12_Resource *texture_resource = (GPU_D12_Resource *)texture;
 
     /* Blit */
     present_blit(swapchain_buffer, texture_resource, texture_xf);
@@ -3327,7 +3327,7 @@ void GPU_PresentSwapchain(GPU_Swapchain *gp_swapchain, Vec2I32 backbuffer_resolu
         for (u32 i = 0; i < countof(g->command_queues); ++i)
         {
             {
-                struct command_queue *cq = g->command_queues[i];
+                GPU_D12_CommandQueue *cq = g->command_queues[i];
                 __prof_dx12_new_frame(cq->prof);
             }
         }
@@ -3337,7 +3337,7 @@ void GPU_PresentSwapchain(GPU_Swapchain *gp_swapchain, Vec2I32 backbuffer_resolu
         __profn("Collect queues");
         for (u32 i = 0; i < countof(g->command_queues); ++i)
         {
-            struct command_queue *cq = g->command_queues[i];
+            GPU_D12_CommandQueue *cq = g->command_queues[i];
             __prof_dx12_collect(cq->prof);
         }
     }
@@ -3363,12 +3363,12 @@ P_JobDef(dx12_evictor_job, _)
 
             /* Copyqueued data */
             u32 num_fenced_releases = 0;
-            struct fenced_release_data *fenced_releases = 0;
+            GPU_D12_FencedReleaseData *fenced_releases = 0;
             {
                 __profn("Copyqueued releases");
                 P_Lock lock = P_LockE(&g->fenced_releases_mutex);
-                num_fenced_releases = g->fenced_releases_arena->pos / sizeof(struct fenced_release_data);
-                fenced_releases = PushStructsNoZero(scratch.arena, struct fenced_release_data, num_fenced_releases);
+                num_fenced_releases = g->fenced_releases_arena->pos / sizeof(GPU_D12_FencedReleaseData);
+                fenced_releases = PushStructsNoZero(scratch.arena, GPU_D12_FencedReleaseData, num_fenced_releases);
                 CopyBytes(fenced_releases, ArenaBase(g->fenced_releases_arena), g->fenced_releases_arena->pos);
                 ResetArena(g->fenced_releases_arena);
                 CopyBytes(targets, g->fenced_release_targets, sizeof(targets));
@@ -3382,7 +3382,7 @@ P_JobDef(dx12_evictor_job, _)
                 {
                     while (completed_targets[i] < targets[i])
                     {
-                        struct command_queue *cq = g->command_queues[i];
+                        GPU_D12_CommandQueue *cq = g->command_queues[i];
                         completed_targets[i] = ID3D12Fence_GetCompletedValue(cq->submit_fence);
                         if (completed_targets[i] < targets[i])
                         {
@@ -3405,7 +3405,7 @@ P_JobDef(dx12_evictor_job, _)
             /* Process releases */
             for (u32 i = 0; i < num_fenced_releases; ++i)
             {
-                struct fenced_release_data *fr = &fenced_releases[i];
+                GPU_D12_FencedReleaseData *fr = &fenced_releases[i];
                 switch (fr->kind)
                 {
                     default:
@@ -3414,15 +3414,15 @@ P_JobDef(dx12_evictor_job, _)
                         Assert(0);
                     } break;
 
-                    case FENCED_RELEASE_KIND_RESOURCE:
+                    case GPU_D12_FencedReleaseKind_Resource:
                     {
-                        struct dx12_resource *resource = (struct dx12_resource *)fr->ptr;
+                        GPU_D12_Resource *resource = (GPU_D12_Resource *)fr->ptr;
                         dx12_resource_release_now(resource);
                     } break;
 
-                    case FENCED_RELEASE_KIND_PIPELINE:
+                    case GPU_D12_FencedReleaseKind_Pipeline:
                     {
-                        struct pipeline *pipeline = (struct pipeline *)fr->ptr;
+                        GPU_D12_Pipeline *pipeline = (GPU_D12_Pipeline *)fr->ptr;
                         pipeline_release_now(pipeline);
                     } break;
                 }
diff --git a/src/gpu/gpu_dx12.h b/src/gpu/gpu_dx12.h
index ce27c7cc..4f964c28 100644
--- a/src/gpu/gpu_dx12.h
+++ b/src/gpu/gpu_dx12.h
@@ -51,19 +51,38 @@
  * structs
  * ========================== */
 
-struct shader_desc
+Struct(GPU_D12_Descriptor)
 {
-    String file;
-    String func;
+    struct GPU_D12_CpuDescriptorHeap *heap;
+
+    u32 index;
+    D3D12_CPU_DESCRIPTOR_HANDLE handle;
+
+    GPU_D12_Descriptor *next_free;
 };
 
-struct pipeline_rtv_desc
+Struct(GPU_D12_Resource)
+{
+    enum D3D12_RESOURCE_STATES state;
+    ID3D12Resource *resource;
+    GPU_D12_Descriptor *cbv_descriptor;
+    GPU_D12_Descriptor *srv_descriptor;
+    GPU_D12_Descriptor *uav_descriptor;
+    GPU_D12_Descriptor *rtv_descriptor;
+
+    D3D12_GPU_VIRTUAL_ADDRESS gpu_address;  /* NOTE: 0 for textures */
+
+    Vec2I32 texture_size;
+    GPU_D12_Resource *next_free;
+};
+
+Struct(GPU_D12_RtvDesc)
 {
     DXGI_FORMAT format;
     b32 blending;
 };
 
-struct pipeline_desc
+Struct(GPU_D12_PipelineDesc)
 {
     String name;
 
@@ -72,10 +91,10 @@ struct pipeline_desc
     String ps_dxc;
     String cs_dxc;
 
-    struct pipeline_rtv_desc rtvs[8];
+    GPU_D12_RtvDesc rtvs[8];
 };
 
-struct pipeline
+Struct(GPU_D12_Pipeline)
 {
     String name;
     u64 hash;
@@ -89,41 +108,28 @@ struct pipeline
 
     ID3D12PipelineState *pso;
     ID3D12RootSignature *rootsig;
-    struct pipeline_desc desc;
+    GPU_D12_PipelineDesc desc;
 
-    struct pipeline *next;
+    GPU_D12_Pipeline *next;
 };
 
-struct pipeline_error
-{
-    String msg;
-    struct pipeline_error *next;
-};
-
-struct pipeline_include
-{
-    String name;
-    u64 name_hash;
-    struct pipeline_include *next;
-};
-
-struct pipeline_scope
+Struct(GPU_D12_PipelineScope)
 {
     Arena *arena;
     Dict *refs;
-    struct pipeline_scope *next_free;
+    GPU_D12_PipelineScope *next_free;
 };
 
-struct command_queue_desc
+Struct(GPU_D12_CommandQueueDesc)
 {
     enum D3D12_COMMAND_LIST_TYPE type;
     enum D3D12_COMMAND_QUEUE_PRIORITY priority;
     String dbg_name;
 };
 
-struct command_queue
+Struct(GPU_D12_CommandQueue)
 {
-    struct command_queue_desc desc;
+    GPU_D12_CommandQueueDesc desc;
     ID3D12CommandQueue *cq;
     Arena *arena;
 
@@ -131,123 +137,98 @@ struct command_queue
     u64 submit_fence_target;
     ID3D12Fence *submit_fence;
 
-    struct command_list_pool *cl_pool;
+    struct GPU_D12_CommandListPool *cl_pool;
 
 #if ProfilingGpu
     __prof_dx12_ctx(prof);
 #endif
 };
 
-struct command_list_pool
+Struct(GPU_D12_CommandListPool)
 {
-    struct command_queue *cq;
+    GPU_D12_CommandQueue *cq;
     Arena *arena;
     P_Mutex mutex;
-    struct command_list *first_submitted_command_list;
-    struct command_list *last_submitted_command_list;
+    struct GPU_D12_CommandList *first_submitted_command_list;
+    struct GPU_D12_CommandList *last_submitted_command_list;
 };
 
-struct command_list
-{
-    struct command_queue *cq;
-    struct command_list_pool *pool;
-    struct ID3D12CommandAllocator *ca;
-    struct ID3D12GraphicsCommandList *cl;
-    P_Lock global_record_lock;
-
-    struct pipeline *cur_pipeline;
-
-    struct command_descriptor_heap *first_command_descriptor_heap;
-    struct command_buffer *first_command_buffer;
-
-    u64 submitted_fence_target;
-    struct command_list *prev_submitted;
-    struct command_list *next_submitted;
-};
-
-struct command_descriptor_heap
+Struct(GPU_D12_CommandDescriptorHeap)
 {
     D3D12_DESCRIPTOR_HEAP_TYPE type;
     ID3D12DescriptorHeap *heap;
     D3D12_CPU_DESCRIPTOR_HANDLE start_cpu_handle;
     D3D12_GPU_DESCRIPTOR_HANDLE start_gpu_handle;
 
-    struct command_descriptor_heap *next_in_command_list;
+    GPU_D12_CommandDescriptorHeap *next_in_command_list;
 
     u64 submitted_fence_target;
-    struct command_queue *submitted_cq;
-    struct command_descriptor_heap *prev_submitted;
-    struct command_descriptor_heap *next_submitted;
+    GPU_D12_CommandQueue *submitted_cq;
+    GPU_D12_CommandDescriptorHeap *prev_submitted;
+    GPU_D12_CommandDescriptorHeap *next_submitted;
 };
 
-struct command_buffer
+Struct(GPU_D12_CommandBuffer)
 {
-    struct command_buffer_group *group;
+    struct GPU_D12_CommandBufferGroup *group;
 
     u64 size;
-    struct dx12_resource *resource;
+    GPU_D12_Resource *resource;
     D3D12_VERTEX_BUFFER_VIEW vbv;
     D3D12_INDEX_BUFFER_VIEW Ibv;
 
-    struct command_buffer *next_in_command_list;
+    GPU_D12_CommandBuffer *next_in_command_list;
 
     u64 submitted_fence_target;
-    struct command_queue *submitted_cq;
-    struct command_buffer *prev_submitted;
-    struct command_buffer *next_submitted;
+    GPU_D12_CommandQueue *submitted_cq;
+    GPU_D12_CommandBuffer *prev_submitted;
+    GPU_D12_CommandBuffer *next_submitted;
 };
 
-struct command_buffer_group
+Struct(GPU_D12_CommandBufferGroup)
 {
-    struct command_buffer *first_submitted;
-    struct command_buffer *last_submitted;
+    GPU_D12_CommandBuffer *first_submitted;
+    GPU_D12_CommandBuffer *last_submitted;
 };
 
-struct descriptor
+Struct(GPU_D12_CommandList)
 {
-    struct cpu_descriptor_heap *heap;
+    GPU_D12_CommandQueue *cq;
+    GPU_D12_CommandListPool *pool;
+    struct ID3D12CommandAllocator *ca;
+    struct ID3D12GraphicsCommandList *cl;
+    P_Lock global_record_lock;
 
-    u32 index;
-    D3D12_CPU_DESCRIPTOR_HANDLE handle;
+    GPU_D12_Pipeline *cur_pipeline;
 
-    struct descriptor *next_free;
+    GPU_D12_CommandDescriptorHeap *first_command_descriptor_heap;
+    GPU_D12_CommandBuffer *first_command_buffer;
+
+    u64 submitted_fence_target;
+    GPU_D12_CommandList *prev_submitted;
+    GPU_D12_CommandList *next_submitted;
 };
 
-struct dx12_resource
+Struct(GPU_D12_SwapchainBuffer)
 {
-    enum D3D12_RESOURCE_STATES state;
+    struct GPU_D12_Swapchain *swapchain;
     ID3D12Resource *resource;
-    struct descriptor *cbv_descriptor;
-    struct descriptor *srv_descriptor;
-    struct descriptor *uav_descriptor;
-    struct descriptor *rtv_descriptor;
-
-    D3D12_GPU_VIRTUAL_ADDRESS gpu_address;  /* NOTE: 0 for textures */
-
-    Vec2I32 texture_size;
-    struct dx12_resource *next_free;
-};
-
-struct swapchain_buffer
-{
-    struct swapchain *swapchain;
-    ID3D12Resource *resource;
-    struct descriptor *rtv_descriptor;
+    GPU_D12_Descriptor *rtv_descriptor;
     D3D12_RESOURCE_STATES state;
 };
 
-struct swapchain
+Struct(GPU_D12_Swapchain)
 {
     IDXGISwapChain3 *swapchain;
     HWND hwnd;
     HANDLE waitable;
     Vec2I32 resolution;
-    struct swapchain_buffer buffers[DX12_SWAPCHAIN_BUFFER_COUNT];
+    GPU_D12_SwapchainBuffer buffers[DX12_SWAPCHAIN_BUFFER_COUNT];
 
-    struct swapchain *next_free;
+    GPU_D12_Swapchain *next_free;
 };
 
-struct cpu_descriptor_heap
+Struct(GPU_D12_CpuDescriptorHeap)
 {
     enum D3D12_DESCRIPTOR_HEAP_TYPE type;
     Arena *arena;
@@ -257,32 +238,32 @@ struct cpu_descriptor_heap
     u32 num_descriptors_reserved;
     u32 num_descriptors_capacity;
 
-    struct descriptor *first_free_descriptor;
+    GPU_D12_Descriptor *first_free_descriptor;
 
     ID3D12DescriptorHeap *heap;
     struct D3D12_CPU_DESCRIPTOR_HANDLE handle;
 };
 
-enum fenced_release_kind
+typedef i32 GPU_D12_FencedReleaseKind; enum
 {
-    FENCED_RELEASE_KIND_NONE,
-    FENCED_RELEASE_KIND_RESOURCE,
-    FENCED_RELEASE_KIND_PIPELINE
+    GPU_D12_FencedReleaseKind_None,
+    GPU_D12_FencedReleaseKind_Resource,
+    GPU_D12_FencedReleaseKind_Pipeline
 };
 
-struct fenced_release_data
+Struct(GPU_D12_FencedReleaseData)
 {
-    enum fenced_release_kind kind;
+    GPU_D12_FencedReleaseKind kind;
     void *ptr;
 };
 
-struct command_queue_alloc_job_sig { struct command_queue_desc *descs_in; struct command_queue **cqs_out; };
+Struct(GPU_D12_AllocCommandQueueJobSig) { GPU_D12_CommandQueueDesc *descs_in; GPU_D12_CommandQueue **cqs_out; };
 
-struct pipeline_alloc_job_sig { struct pipeline_desc *descs_in; struct pipeline **pipelines_out; };
+Struct(GPU_D12_AllocPipelineJobSig) { GPU_D12_PipelineDesc *descs_in; GPU_D12_Pipeline **pipelines_out; };
 
-struct dx12_upload_job_sig { struct dx12_resource *resource; void *data; };
+Struct(GPU_D12_UploadJobSig) { GPU_D12_Resource *resource; void *data; };
 
-struct shader_compile_desc
+Struct(GPU_D12_ShaderDesc)
 {
     String src;
     String friendly_name;
@@ -290,7 +271,7 @@ struct shader_compile_desc
     String target;
 };
 
-struct shader_compile_result
+Struct(GPU_D12_CompiledShaderResult)
 {
     i64 elapsed_ns;
     String dxc;
@@ -298,15 +279,15 @@ struct shader_compile_result
     b32 success;
 };
 
-struct shader_compile_job_sig
+Struct(GPU_D12_CompileShaderJobSig)
 {
     Arena *arena;
-    struct shader_compile_desc *descs;
-    struct shader_compile_result *results;
+    GPU_D12_ShaderDesc *descs;
+    GPU_D12_CompiledShaderResult *results;
 };
 
 
-struct render_sig
+Struct(GPU_D12_RenderSig)
 {
     Arena *arena;
     RandState rand;
@@ -329,16 +310,16 @@ struct render_sig
     Arena *material_grid_descs_arena;
 
     /* Resources */
-    struct dx12_resource *albedo;
-    struct dx12_resource *emittance;
-    struct dx12_resource *emittance_flood_read;
-    struct dx12_resource *emittance_flood_target;
-    struct dx12_resource *shade_read;
-    struct dx12_resource *shade_target;
-    struct dx12_resource *ui_target;
+    GPU_D12_Resource *albedo;
+    GPU_D12_Resource *emittance;
+    GPU_D12_Resource *emittance_flood_read;
+    GPU_D12_Resource *emittance_flood_target;
+    GPU_D12_Resource *shade_read;
+    GPU_D12_Resource *shade_target;
+    GPU_D12_Resource *ui_target;
 };
 
-struct material_instance_desc
+Struct(GPU_D12_MaterialInstanceDesc)
 {
     Xform xf;
     u32 texture_id;
@@ -349,7 +330,7 @@ struct material_instance_desc
     u32 grid_id;
 };
 
-struct ui_rect_instance_desc
+Struct(GPU_D12_UiRectInstanceDesc)
 {
     Xform xf;
     u32 texture_id;
@@ -357,7 +338,7 @@ struct ui_rect_instance_desc
     u32 tint;
 };
 
-struct material_grid_desc
+Struct(GPU_D12_MaterialGridDesc)
 {
     f32 line_thickness;
     f32 line_spacing;
@@ -380,8 +361,8 @@ Struct(GPU_D12_SharedState)
     /* Descriptor heaps pool */
     P_Mutex command_descriptor_heaps_mutex;
     Arena *command_descriptor_heaps_arena;
-    struct command_descriptor_heap *first_submitted_command_descriptor_heap;
-    struct command_descriptor_heap *last_submitted_command_descriptor_heap;
+    GPU_D12_CommandDescriptorHeap *first_submitted_command_descriptor_heap;
+    GPU_D12_CommandDescriptorHeap *last_submitted_command_descriptor_heap;
 
     /* Command buffers pool */
     P_Mutex command_buffers_mutex;
@@ -391,12 +372,12 @@ Struct(GPU_D12_SharedState)
     /* Resources pool */
     P_Mutex resources_mutex;
     Arena *resources_arena;
-    struct dx12_resource *first_free_resource;
+    GPU_D12_Resource *first_free_resource;
 
     /* Swapchains pool */
     P_Mutex swapchains_mutex;
     Arena *swapchains_arena;
-    struct swapchain *first_free_swapchain;
+    GPU_D12_Swapchain *first_free_swapchain;
 
     /* Shader bytecode archive */
     TAR_Archive dxc_archive;
@@ -404,11 +385,11 @@ Struct(GPU_D12_SharedState)
     /* Pipeline cache */
     P_Mutex pipelines_mutex;
     Arena *pipelines_arena;
-    struct pipeline *first_free_pipeline;
+    GPU_D12_Pipeline *first_free_pipeline;
     Dict *pipeline_descs;
     Dict *top_pipelines;  /* Latest pipelines */
     Dict *top_successful_pipelines;  /* Latest pipelines that successfully compiled */
-    struct pipeline_scope *first_free_pipeline_scope;
+    GPU_D12_PipelineScope *first_free_pipeline_scope;
 
     /* Fenced release queue */
     P_Mutex fenced_releases_mutex;
@@ -429,13 +410,13 @@ Struct(GPU_D12_SharedState)
     u32 desc_counts[D3D12_DESCRIPTOR_HEAP_TYPE_NUM_TYPES];
 
     /* Global descriptor heaps */
-    struct cpu_descriptor_heap *cbv_srv_uav_heap;
-    struct cpu_descriptor_heap *rtv_heap;
+    GPU_D12_CpuDescriptorHeap *cbv_srv_uav_heap;
+    GPU_D12_CpuDescriptorHeap *rtv_heap;
 
     /* Command queues */
     P_Mutex global_command_list_record_mutex;
     P_Mutex global_submit_mutex;
-    struct command_queue *command_queues[DX12_NUM_QUEUES];
+    GPU_D12_CommandQueue *command_queues[DX12_NUM_QUEUES];
 
     /* Evictor job */
     P_Counter evictor_job_counter;
@@ -493,20 +474,20 @@ P_JobDef(shader_compile_job, job);
 
     P_JobDef(pipeline_alloc_job, job);
 
-void pipeline_release_now(struct pipeline *pipeline);
+void pipeline_release_now(GPU_D12_Pipeline *pipeline);
 
 /* ========================== *
  * Pipeline cache
  * ========================== */
 
-struct pipeline_scope *pipeline_scope_begin(void);
+GPU_D12_PipelineScope *pipeline_scope_begin(void);
 
-void pipeline_scope_end(struct pipeline_scope *scope);
+void pipeline_scope_end(GPU_D12_PipelineScope *scope);
 
-extern Readonly struct pipeline g_nil_pipeline;
-struct pipeline *pipeline_from_name(struct pipeline_scope *scope, String name);
+extern Readonly GPU_D12_Pipeline g_nil_pipeline;
+GPU_D12_Pipeline *pipeline_from_name(GPU_D12_PipelineScope *scope, String name);
 
-void pipeline_register(u64 num_pipelines, struct pipeline **pipelines);
+void pipeline_register(u64 num_pipelines, GPU_D12_Pipeline **pipelines);
 
 W_CallbackFuncDef(pipeline_watch_callback, name);
 
@@ -514,29 +495,29 @@ W_CallbackFuncDef(pipeline_watch_callback, name);
  * Descriptor
  * ========================== */
 
-struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh);
+GPU_D12_Descriptor *descriptor_alloc(GPU_D12_CpuDescriptorHeap *dh);
 
-void descriptor_release(struct descriptor *descriptor);
+void descriptor_release(GPU_D12_Descriptor *descriptor);
 
 /* ========================== *
  * CPU descriptor heap
  * ========================== */
 
-struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
+GPU_D12_CpuDescriptorHeap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
 
 /* ========================== *
  * Fenced release
  * ========================== */
 
-void fenced_release(void *data, enum fenced_release_kind kind);
+void fenced_release(void *data, GPU_D12_FencedReleaseKind kind);
 
 /* ========================== *
  * Resource
  * ========================== */
 
-struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state);
+GPU_D12_Resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_props, D3D12_HEAP_FLAGS heap_flags, D3D12_RESOURCE_DESC desc, D3D12_RESOURCE_STATES initial_state);
 
-void dx12_resource_release_now(struct dx12_resource *t);
+void dx12_resource_release_now(GPU_D12_Resource *t);
 
 void GPU_ReleaseResource(GPU_Resource *resource);
 
@@ -547,7 +528,7 @@ void GPU_ReleaseResource(GPU_Resource *resource);
 struct dx12_resource_barrier_desc
 {
     enum D3D12_RESOURCE_BARRIER_TYPE type;
-    struct dx12_resource *resource;
+    GPU_D12_Resource *resource;
     enum D3D12_RESOURCE_STATES new_state;  /* 0 if type != D3D12_RESOURCE_BARRIER_TYPE_TRANSITION */
 };
 
@@ -559,24 +540,24 @@ void dx12_resource_barriers(ID3D12GraphicsCommandList *cl, i32 num_descs, struct
 
 P_JobDef(command_queue_alloc_job, job);
 
-void command_queue_release(struct command_queue *cq);
+void command_queue_release(GPU_D12_CommandQueue *cq);
 
 /* ========================== *
  * Command list
  * ========================== */
 
-struct command_list_pool *command_list_pool_alloc(struct command_queue *cq);
+GPU_D12_CommandListPool *command_list_pool_alloc(GPU_D12_CommandQueue *cq);
 
-struct command_list *command_list_open(struct command_list_pool *pool);
+GPU_D12_CommandList *command_list_open(GPU_D12_CommandListPool *pool);
 
 /* TODO: Allow multiple command list submissions */
-u64 command_list_close(struct command_list *cl);
+u64 command_list_close(GPU_D12_CommandList *cl);
 
 /* ========================== *
  * Command descriptor heap (GPU / shader visible descriptor heap)
  * ========================== */
 
-struct command_descriptor_heap *command_list_push_descriptor_heap(struct command_list *cl, struct cpu_descriptor_heap *dh_cpu);
+GPU_D12_CommandDescriptorHeap *command_list_push_descriptor_heap(GPU_D12_CommandList *cl, GPU_D12_CpuDescriptorHeap *dh_cpu);
 
 /* ========================== *
  * Command buffer
@@ -587,7 +568,7 @@ u64 command_buffer_hash_from_size(u64 size);
 u64 align_up_pow2(u64 v);
 
 #define command_list_push_buffer(cl, count, elems) _command_list_push_buffer((cl), count * ((elems) ? sizeof(*(elems)) : 0), (elems), (elems) ? sizeof(*(elems)) : 1)
-struct command_buffer *_command_list_push_buffer(struct command_list *cl, u64 data_len, void *data, u64 data_stride);
+GPU_D12_CommandBuffer *_command_list_push_buffer(GPU_D12_CommandList *cl, u64 data_len, void *data, u64 data_stride);
 
 /* ========================== *
  * Wait job
@@ -619,33 +600,33 @@ P_JobDef(dx12_upload_job, job);
  * Run utils
  * ========================== */
 
-void command_list_set_pipeline(struct command_list *cl, struct pipeline *pipeline);
+void command_list_set_pipeline(GPU_D12_CommandList *cl, GPU_D12_Pipeline *pipeline);
 
 
-void command_list_set_sig(struct command_list *cl, void *src, u32 size);
+void command_list_set_sig(GPU_D12_CommandList *cl, void *src, u32 size);
 
 struct D3D12_VIEWPORT viewport_from_rect(Rect r);
 
 D3D12_RECT scissor_from_rect(Rect r);
 
-D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(struct command_buffer *cb, u32 vertex_size);
+D3D12_VERTEX_BUFFER_VIEW vbv_from_command_buffer(GPU_D12_CommandBuffer *cb, u32 vertex_size);
 
-D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(struct command_buffer *cb, DXGI_FORMAT format);
+D3D12_INDEX_BUFFER_VIEW ibv_from_command_buffer(GPU_D12_CommandBuffer *cb, DXGI_FORMAT format);
 
-struct dx12_resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state);
+GPU_D12_Resource *gbuff_alloc(DXGI_FORMAT format, Vec2I32 size, D3D12_RESOURCE_STATES initial_state);
 
 /* Calculate the view projection matrix */
 Inline Mat4x4 calculate_vp(Xform view, f32 viewport_width, f32 viewport_height);
 
-D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(struct descriptor *descriptor, struct command_descriptor_heap *cdh);
+D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle_from_descriptor(GPU_D12_Descriptor *descriptor, GPU_D12_CommandDescriptorHeap *cdh);
 
 /* ========================== *
  * Render sig
  * ========================== */
 
-struct render_sig *render_sig_alloc(void);
+GPU_D12_RenderSig *render_sig_alloc(void);
 
-void render_sig_reset(struct render_sig *sig);
+void render_sig_reset(GPU_D12_RenderSig *sig);
 
 GPU_RenderSig *GPU_AllocRenderSig(void);
 
@@ -667,7 +648,7 @@ GPU_MemoryInfo GPU_QueryMemoryInfo(void);
  * Swapchain
  * ========================== */
 
-void swapchain_init_resources(struct swapchain *swapchain);
+void swapchain_init_resources(GPU_D12_Swapchain *swapchain);
 
 GPU_Swapchain *GPU_AllocSwapchain(P_Window *window, Vec2I32 resolution);
 
@@ -675,13 +656,13 @@ void GPU_ReleaseSwapchain(GPU_Swapchain *gp_swapchain);
 
 void GPU_WaitOnSwapchain(GPU_Swapchain *gp_swapchain);
 
-struct swapchain_buffer *update_swapchain(struct swapchain *swapchain, Vec2I32 resolution);
+GPU_D12_SwapchainBuffer *update_swapchain(GPU_D12_Swapchain *swapchain, Vec2I32 resolution);
 
 /* ========================== *
  * Present
  * ========================== */
 
-void present_blit(struct swapchain_buffer *dst, struct dx12_resource *src, Xform src_xf);
+void present_blit(GPU_D12_SwapchainBuffer *dst, GPU_D12_Resource *src, Xform src_xf);
 
 void GPU_PresentSwapchain(GPU_Swapchain *gp_swapchain, Vec2I32 backbuffer_resolution, GPU_Resource *texture, Xform texture_xf, i32 vsync);