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jacob 2025-06-17 23:31:50 -05:00
parent b50ba7d4e2
commit 657e48d7b1
2 changed files with 16 additions and 16 deletions
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2
src/config.h
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@ -80,7 +80,7 @@
#define DX12_TEST 0 #define DX12_TEST 1

30
src/gpu_dx12.c
View File

@ -82,7 +82,7 @@ struct pipeline_error {
struct command_queue { struct command_queue {
struct arena *arena; struct arena *arena;
struct sys_mutex mutex; struct sys_mutex *mutex;
ID3D12CommandQueue *cq; ID3D12CommandQueue *cq;
}; };
@ -116,7 +116,7 @@ struct dx12_resource {
struct cpu_descriptor_heap { struct cpu_descriptor_heap {
enum D3D12_DESCRIPTOR_HEAP_TYPE type; enum D3D12_DESCRIPTOR_HEAP_TYPE type;
struct arena *arena; struct arena *arena;
struct sys_mutex mutex; struct sys_mutex *mutex;
u32 descriptor_size; u32 descriptor_size;
u32 num_descriptors_reserved; u32 num_descriptors_reserved;
@ -165,19 +165,19 @@ struct handle_entry {
GLOBAL struct { GLOBAL struct {
/* Handles pool */ /* Handles pool */
struct sys_mutex handle_entries_mutex; struct sys_mutex *handle_entries_mutex;
struct arena *handle_entries_arena; struct arena *handle_entries_arena;
struct handle_entry *first_free_handle_entry; struct handle_entry *first_free_handle_entry;
u64 num_handle_entries_reserved; u64 num_handle_entries_reserved;
/* Descriptor heaps pool */ /* Descriptor heaps pool */
struct sys_mutex gpu_descriptor_heaps_mutex; struct sys_mutex *gpu_descriptor_heaps_mutex;
struct arena *gpu_descriptor_heaps_arena; struct arena *gpu_descriptor_heaps_arena;
struct gpu_descriptor_heap *first_free_gpu_descriptor_heap; struct gpu_descriptor_heap *first_free_gpu_descriptor_heap;
struct gpu_descriptor_heap *last_free_gpu_descriptor_heap; struct gpu_descriptor_heap *last_free_gpu_descriptor_heap;
/* Resources pool */ /* Resources pool */
struct sys_mutex resources_mutex; struct sys_mutex *resources_mutex;
struct arena *resources_arena; struct arena *resources_arena;
struct dx12_resource *first_free_resource; struct dx12_resource *first_free_resource;
@ -369,7 +369,7 @@ INTERNAL struct gpu_handle handle_alloc(enum handle_kind kind, void *data)
u64 idx = 0; u64 idx = 0;
struct handle_entry *entry = NULL; struct handle_entry *entry = NULL;
{ {
struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex); struct sys_lock lock = sys_mutex_lock_e(G.handle_entries_mutex);
if (G.first_free_handle_entry) { if (G.first_free_handle_entry) {
entry = G.first_free_handle_entry; entry = G.first_free_handle_entry;
G.first_free_handle_entry = entry->next_free; G.first_free_handle_entry = entry->next_free;
@ -395,10 +395,10 @@ INTERNAL struct gpu_handle handle_alloc(enum handle_kind kind, void *data)
INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct sys_lock *lock) INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct sys_lock *lock)
{ {
sys_assert_locked_e_or_s(lock, &G.handle_entries_mutex); sys_assert_locked_e_or_s(lock, G.handle_entries_mutex);
struct handle_entry *res = NULL; struct handle_entry *res = NULL;
if (handle.idx > 0 && handle.idx < G.num_handle_entries_reserved) { if (handle.idx > 0 && handle.idx < G.num_handle_entries_reserved) {
struct handle_entry *tmp = &((struct handle_entry *)G.handle_entries_arena->base)[handle.idx]; struct handle_entry *tmp = &((struct handle_entry *)arena_base(G.handle_entries_arena))[handle.idx];
if (tmp->gen == handle.gen) { if (tmp->gen == handle.gen) {
res = tmp; res = tmp;
} }
@ -409,7 +409,7 @@ INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct
INTERNAL void *handle_get_data(struct gpu_handle handle, enum handle_kind kind) INTERNAL void *handle_get_data(struct gpu_handle handle, enum handle_kind kind)
{ {
void *data = NULL; void *data = NULL;
struct sys_lock lock = sys_mutex_lock_s(&G.handle_entries_mutex); struct sys_lock lock = sys_mutex_lock_s(G.handle_entries_mutex);
{ {
struct handle_entry *entry = handle_get_entry(handle, &lock); struct handle_entry *entry = handle_get_entry(handle, &lock);
data = entry->data; data = entry->data;
@ -431,7 +431,7 @@ void gpu_release(struct gpu_handle handle)
void *data = NULL; void *data = NULL;
/* Release handle entry */ /* Release handle entry */
struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex); struct sys_lock lock = sys_mutex_lock_e(G.handle_entries_mutex);
{ {
struct handle_entry *entry = handle_get_entry(handle, &lock); struct handle_entry *entry = handle_get_entry(handle, &lock);
if (entry) { if (entry) {
@ -1271,7 +1271,7 @@ INTERNAL struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh)
struct descriptor *d = NULL; struct descriptor *d = NULL;
D3D12_CPU_DESCRIPTOR_HANDLE handle = ZI; D3D12_CPU_DESCRIPTOR_HANDLE handle = ZI;
{ {
struct sys_lock lock = sys_mutex_lock_e(&dh->mutex); struct sys_lock lock = sys_mutex_lock_e(dh->mutex);
if (dh->first_free_descriptor) { if (dh->first_free_descriptor) {
d = dh->first_free_descriptor; d = dh->first_free_descriptor;
handle = d->handle; handle = d->handle;
@ -1308,7 +1308,7 @@ INTERNAL struct gpu_descriptor_heap *gpu_descriptor_heap_alloc(struct cpu_descri
ID3D12Fence *free_fence = NULL; ID3D12Fence *free_fence = NULL;
u64 free_fence_value = 0; u64 free_fence_value = 0;
{ {
struct sys_lock lock = sys_mutex_lock_e(&G.gpu_descriptor_heaps_mutex); struct sys_lock lock = sys_mutex_lock_e(G.gpu_descriptor_heaps_mutex);
/* Find first free & ready heap for reuse */ /* Find first free & ready heap for reuse */
/* FIXME: Rather than storing fence per heap, store & increment fence per queue and check against it */ /* FIXME: Rather than storing fence per heap, store & increment fence per queue and check against it */
for (struct gpu_descriptor_heap *tmp = G.first_free_gpu_descriptor_heap; tmp; tmp = tmp->next_free) { for (struct gpu_descriptor_heap *tmp = G.first_free_gpu_descriptor_heap; tmp; tmp = tmp->next_free) {
@ -1370,7 +1370,7 @@ INTERNAL struct gpu_descriptor_heap *gpu_descriptor_heap_alloc(struct cpu_descri
/* Copy CPU heap */ /* Copy CPU heap */
{ {
struct sys_lock lock = sys_mutex_lock_s(&dh_cpu->mutex); struct sys_lock lock = sys_mutex_lock_s(dh_cpu->mutex);
ID3D12Device_CopyDescriptorsSimple(G.device, dh_cpu->num_descriptors_reserved, dh_gpu->cpu_handle, dh_cpu->handle, D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV); ID3D12Device_CopyDescriptorsSimple(G.device, dh_cpu->num_descriptors_reserved, dh_gpu->cpu_handle, dh_cpu->handle, D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);
sys_mutex_unlock(&lock); sys_mutex_unlock(&lock);
} }
@ -1384,7 +1384,7 @@ INTERNAL void gpu_descriptor_heap_release(struct command_queue *cq, struct gpu_d
++dh->free_fence_value; ++dh->free_fence_value;
ID3D12CommandQueue_Signal(cq->cq, dh->free_fence, dh->free_fence_value); ID3D12CommandQueue_Signal(cq->cq, dh->free_fence, dh->free_fence_value);
/* Add to free list */ /* Add to free list */
struct sys_lock lock = sys_mutex_lock_e(&G.gpu_descriptor_heaps_mutex); struct sys_lock lock = sys_mutex_lock_e(G.gpu_descriptor_heaps_mutex);
dh->next_free = G.first_free_gpu_descriptor_heap; dh->next_free = G.first_free_gpu_descriptor_heap;
if (G.last_free_gpu_descriptor_heap) { if (G.last_free_gpu_descriptor_heap) {
G.last_free_gpu_descriptor_heap->next_free = dh; G.last_free_gpu_descriptor_heap->next_free = dh;
@ -1475,7 +1475,7 @@ INTERNAL struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_pr
{ {
struct dx12_resource *r = NULL; struct dx12_resource *r = NULL;
{ {
struct sys_lock lock = sys_mutex_lock_e(&G.resources_mutex); struct sys_lock lock = sys_mutex_lock_e(G.resources_mutex);
if (G.first_free_resource) { if (G.first_free_resource) {
r = G.first_free_resource; r = G.first_free_resource;
G.first_free_resource = r->next_free; G.first_free_resource = r->next_free;