From 657e48d7b13514b224cfa9cc2db1de4715318606 Mon Sep 17 00:00:00 2001 From: jacob Date: Tue, 17 Jun 2025 23:31:50 -0500 Subject: [PATCH] formatting --- src/config.h | 2 +- src/gpu_dx12.c | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/config.h b/src/config.h index 3496649b..3b07856b 100644 --- a/src/config.h +++ b/src/config.h @@ -80,7 +80,7 @@ -#define DX12_TEST 0 +#define DX12_TEST 1 diff --git a/src/gpu_dx12.c b/src/gpu_dx12.c index e3bfdf8f..1287cfc2 100644 --- a/src/gpu_dx12.c +++ b/src/gpu_dx12.c @@ -82,7 +82,7 @@ struct pipeline_error { struct command_queue { struct arena *arena; - struct sys_mutex mutex; + struct sys_mutex *mutex; ID3D12CommandQueue *cq; }; @@ -116,7 +116,7 @@ struct dx12_resource { struct cpu_descriptor_heap { enum D3D12_DESCRIPTOR_HEAP_TYPE type; struct arena *arena; - struct sys_mutex mutex; + struct sys_mutex *mutex; u32 descriptor_size; u32 num_descriptors_reserved; @@ -165,19 +165,19 @@ struct handle_entry { GLOBAL struct { /* Handles pool */ - struct sys_mutex handle_entries_mutex; + struct sys_mutex *handle_entries_mutex; struct arena *handle_entries_arena; struct handle_entry *first_free_handle_entry; u64 num_handle_entries_reserved; /* Descriptor heaps pool */ - struct sys_mutex gpu_descriptor_heaps_mutex; + struct sys_mutex *gpu_descriptor_heaps_mutex; struct arena *gpu_descriptor_heaps_arena; struct gpu_descriptor_heap *first_free_gpu_descriptor_heap; struct gpu_descriptor_heap *last_free_gpu_descriptor_heap; /* Resources pool */ - struct sys_mutex resources_mutex; + struct sys_mutex *resources_mutex; struct arena *resources_arena; struct dx12_resource *first_free_resource; @@ -369,7 +369,7 @@ INTERNAL struct gpu_handle handle_alloc(enum handle_kind kind, void *data) u64 idx = 0; struct handle_entry *entry = NULL; { - struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex); + struct sys_lock lock = sys_mutex_lock_e(G.handle_entries_mutex); if (G.first_free_handle_entry) { entry = G.first_free_handle_entry; G.first_free_handle_entry = entry->next_free; @@ -395,10 +395,10 @@ INTERNAL struct gpu_handle handle_alloc(enum handle_kind kind, void *data) INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct sys_lock *lock) { - sys_assert_locked_e_or_s(lock, &G.handle_entries_mutex); + sys_assert_locked_e_or_s(lock, G.handle_entries_mutex); struct handle_entry *res = NULL; if (handle.idx > 0 && handle.idx < G.num_handle_entries_reserved) { - struct handle_entry *tmp = &((struct handle_entry *)G.handle_entries_arena->base)[handle.idx]; + struct handle_entry *tmp = &((struct handle_entry *)arena_base(G.handle_entries_arena))[handle.idx]; if (tmp->gen == handle.gen) { res = tmp; } @@ -409,7 +409,7 @@ INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct INTERNAL void *handle_get_data(struct gpu_handle handle, enum handle_kind kind) { void *data = NULL; - struct sys_lock lock = sys_mutex_lock_s(&G.handle_entries_mutex); + struct sys_lock lock = sys_mutex_lock_s(G.handle_entries_mutex); { struct handle_entry *entry = handle_get_entry(handle, &lock); data = entry->data; @@ -431,7 +431,7 @@ void gpu_release(struct gpu_handle handle) void *data = NULL; /* Release handle entry */ - struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex); + struct sys_lock lock = sys_mutex_lock_e(G.handle_entries_mutex); { struct handle_entry *entry = handle_get_entry(handle, &lock); if (entry) { @@ -1271,7 +1271,7 @@ INTERNAL struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh) struct descriptor *d = NULL; D3D12_CPU_DESCRIPTOR_HANDLE handle = ZI; { - struct sys_lock lock = sys_mutex_lock_e(&dh->mutex); + struct sys_lock lock = sys_mutex_lock_e(dh->mutex); if (dh->first_free_descriptor) { d = dh->first_free_descriptor; handle = d->handle; @@ -1308,7 +1308,7 @@ INTERNAL struct gpu_descriptor_heap *gpu_descriptor_heap_alloc(struct cpu_descri ID3D12Fence *free_fence = NULL; u64 free_fence_value = 0; { - struct sys_lock lock = sys_mutex_lock_e(&G.gpu_descriptor_heaps_mutex); + struct sys_lock lock = sys_mutex_lock_e(G.gpu_descriptor_heaps_mutex); /* Find first free & ready heap for reuse */ /* FIXME: Rather than storing fence per heap, store & increment fence per queue and check against it */ for (struct gpu_descriptor_heap *tmp = G.first_free_gpu_descriptor_heap; tmp; tmp = tmp->next_free) { @@ -1370,7 +1370,7 @@ INTERNAL struct gpu_descriptor_heap *gpu_descriptor_heap_alloc(struct cpu_descri /* Copy CPU heap */ { - struct sys_lock lock = sys_mutex_lock_s(&dh_cpu->mutex); + struct sys_lock lock = sys_mutex_lock_s(dh_cpu->mutex); ID3D12Device_CopyDescriptorsSimple(G.device, dh_cpu->num_descriptors_reserved, dh_gpu->cpu_handle, dh_cpu->handle, D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV); sys_mutex_unlock(&lock); } @@ -1384,7 +1384,7 @@ INTERNAL void gpu_descriptor_heap_release(struct command_queue *cq, struct gpu_d ++dh->free_fence_value; ID3D12CommandQueue_Signal(cq->cq, dh->free_fence, dh->free_fence_value); /* Add to free list */ - struct sys_lock lock = sys_mutex_lock_e(&G.gpu_descriptor_heaps_mutex); + struct sys_lock lock = sys_mutex_lock_e(G.gpu_descriptor_heaps_mutex); dh->next_free = G.first_free_gpu_descriptor_heap; if (G.last_free_gpu_descriptor_heap) { G.last_free_gpu_descriptor_heap->next_free = dh; @@ -1475,7 +1475,7 @@ INTERNAL struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_pr { struct dx12_resource *r = NULL; { - struct sys_lock lock = sys_mutex_lock_e(&G.resources_mutex); + struct sys_lock lock = sys_mutex_lock_e(G.resources_mutex); if (G.first_free_resource) { r = G.first_free_resource; G.first_free_resource = r->next_free;