From 9aad25a6992a0adf416bdcd0add0b508e294cd1d Mon Sep 17 00:00:00 2001
From: jacob <jacob@cagori.com>
Date: Tue, 17 Jun 2025 18:46:43 -0500
Subject: [PATCH] remove dispatch_state

---
 src/gpu.h      |   4 +-
 src/gpu_dx11.c | 123 +++++++++---------------------
 src/gpu_dx12.c | 197 +++++++++++++++++++++++--------------------------
 src/user.c     |  12 +--
 4 files changed, 129 insertions(+), 207 deletions(-)

diff --git a/src/gpu.h b/src/gpu.h
index 264670ab..afcd80c8 100644
--- a/src/gpu.h
+++ b/src/gpu.h
@@ -126,9 +126,7 @@ struct gpu_dispatch_params {
     struct xform draw_target_view;
 };
 
-struct gpu_handle gpu_dispatch_state_alloc(void);
-
-void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_params params);
+void gpu_dispatch(struct gpu_dispatch_params params);
 
 /* ========================== *
  * Present
diff --git a/src/gpu_dx11.c b/src/gpu_dx11.c
index b4939852..4c81bcb3 100644
--- a/src/gpu_dx11.c
+++ b/src/gpu_dx11.c
@@ -79,7 +79,6 @@ enum dx11_handle_kind {
     DX11_HANDLE_KIND_NONE,
     DX11_HANDLE_KIND_TEXTURE,
     DX11_HANDLE_KIND_PLAN,
-    DX11_HANDLE_KIND_DISPATCH_STATE,
 
     NUM_DX11_HANDLE_KINDS
 };
@@ -96,15 +95,6 @@ struct dx11_shader {
     ID3D11PixelShader *ps;
 };
 
-struct dx11_dispatch_state {
-    struct dx11_handle_header header;
-
-    struct dx11_texture *albedo;
-    struct dx11_buffer *constant_buffer;
-
-    struct dx11_dispatch_state *next_free;
-};
-
 struct dx11_buffer {
     D3D11_BUFFER_DESC desc;
 
@@ -194,7 +184,9 @@ struct dx11_plan {
         struct {
             struct dx11_buffer *instance_buffer;
         } test;
-    } buffers;
+    } cmd_buffers;
+
+    struct dx11_buffer *constant_buffer;
 
     struct dx11_plan *next_free;
 };
@@ -243,9 +235,6 @@ GLOBAL struct {
     struct dx11_texture backbuffer_texture;
     i64 last_backbuffer_resize_ns;
 
-    struct gpu_handle present_blit_plan;
-    struct gpu_handle present_blit_dispatch_state;
-
     ID3D11BlendState *blend_state;
     ID3D11RasterizerState *rasterizer_state;
     ID3D11DepthStencilState *depth_stencil_state;
@@ -279,6 +268,9 @@ GLOBAL struct {
     struct dx11_buffer *dummy_vertex_buffer;
     struct dx11_buffer *quad_index_buffer;
 
+    /* Blit plan */
+    struct gpu_handle present_blit_plan;
+
 } G = ZI, DEBUG_ALIAS(G, G_gpu_dx11);
 
 /* ========================== *
@@ -548,7 +540,6 @@ struct gpu_startup_receipt gpu_startup(struct work_startup_receipt *work_sr, str
 #endif
 
     G.present_blit_plan = gpu_plan_alloc();
-    G.present_blit_dispatch_state = gpu_dispatch_state_alloc();
 
     return (struct gpu_startup_receipt) { 0 };
 }
@@ -587,12 +578,6 @@ void gpu_release(struct gpu_handle handle)
             /* TODO */
             ASSERT(false);
         } break;
-
-        case DX11_HANDLE_KIND_DISPATCH_STATE:
-        {
-            /* TODO */
-            ASSERT(false);
-        } break;
     }
 }
 
@@ -1354,29 +1339,29 @@ struct gpu_handle gpu_plan_alloc(void)
             idesc.BindFlags = D3D11_BIND_INDEX_BUFFER;
             idesc.CPUAccessFlags = D3D11_CPU_ACCESS_WRITE;
 
-            plan->buffers.mesh.vertex_buffer = dx11_buffer_alloc(vdesc, NULL);
-            plan->buffers.mesh.index_buffer = dx11_buffer_alloc(idesc, NULL);
+            plan->cmd_buffers.mesh.vertex_buffer = dx11_buffer_alloc(vdesc, NULL);
+            plan->cmd_buffers.mesh.index_buffer = dx11_buffer_alloc(idesc, NULL);
         }
 
         /* Texture buffers */
         {
             struct D3D11_BUFFER_DESC desc = structured_buffer_desc;
             desc.StructureByteStride = sizeof(struct dx11_texture_instance);
-            plan->buffers.texture.instance_buffer = dx11_buffer_alloc(desc, NULL);
+            plan->cmd_buffers.texture.instance_buffer = dx11_buffer_alloc(desc, NULL);
         }
 
         /* Grid buffers */
         {
             struct D3D11_BUFFER_DESC desc = structured_buffer_desc;
             desc.StructureByteStride = sizeof(struct dx11_grid_instance);
-            plan->buffers.grid.instance_buffer = dx11_buffer_alloc(desc, NULL);
+            plan->cmd_buffers.grid.instance_buffer = dx11_buffer_alloc(desc, NULL);
         }
 
         /* Test buffers */
         {
             struct D3D11_BUFFER_DESC desc = structured_buffer_desc;
             desc.StructureByteStride = sizeof(struct dx11_test_instance);
-            plan->buffers.test.instance_buffer = dx11_buffer_alloc(desc, NULL);
+            plan->cmd_buffers.test.instance_buffer = dx11_buffer_alloc(desc, NULL);
         }
     }
 
@@ -1410,8 +1395,8 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
                 /* TODO: Better count method */
                 cmd = arena_push(&plan->cpu_cmds_arena, struct dx11_cmd);
                 cmd->kind = params.kind;
-                cmd->mesh.vertex_offset = (plan->buffers.mesh.vertex_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_mesh_vertex));
-                cmd->mesh.index_offset = (plan->buffers.mesh.index_buffer->cpu_buffer_arena.pos / sizeof(u32));
+                cmd->mesh.vertex_offset = (plan->cmd_buffers.mesh.vertex_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_mesh_vertex));
+                cmd->mesh.index_offset = (plan->cmd_buffers.mesh.index_buffer->cpu_buffer_arena.pos / sizeof(u32));
                 if (plan->cpu_last_cmd) {
                     plan->cpu_last_cmd->next = cmd;
                 } else {
@@ -1424,7 +1409,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
             u64 vertex_count = params.mesh.vertices.count;
             u64 start_index = cmd->mesh.vertex_count;
             cmd->mesh.vertex_count += vertex_count;
-            struct dx11_mesh_vertex *verts = dx11_buffer_push(plan->buffers.mesh.vertex_buffer, sizeof(struct dx11_mesh_vertex) * vertex_count);
+            struct dx11_mesh_vertex *verts = dx11_buffer_push(plan->cmd_buffers.mesh.vertex_buffer, sizeof(struct dx11_mesh_vertex) * vertex_count);
             for (u64 i = 0; i < vertex_count; ++i) {
                 struct dx11_mesh_vertex *vert = &verts[i];
                 vert->pos = params.mesh.vertices.points[i];
@@ -1433,7 +1418,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
 
             /* Push indices */
             u64 index_count = params.mesh.indices.count;
-            u32 *indices = dx11_buffer_push(plan->buffers.mesh.index_buffer, sizeof(u32) * index_count);
+            u32 *indices = dx11_buffer_push(plan->cmd_buffers.mesh.index_buffer, sizeof(u32) * index_count);
             cmd->mesh.index_count += index_count;
             for (u64 i = 0; i < index_count; ++i) {
                 indices[i] = start_index + params.mesh.indices.indices[i];
@@ -1458,7 +1443,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
                 cmd->kind = params.kind;
                 cmd->texture.sprite = params.texture.sprite;
                 cmd->texture.texture = params.texture.texture;
-                cmd->texture.instance_offset = (plan->buffers.texture.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_texture_instance));
+                cmd->texture.instance_offset = (plan->cmd_buffers.texture.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_texture_instance));
                 if (plan->cpu_last_cmd) {
                     plan->cpu_last_cmd->next = cmd;
                 } else {
@@ -1469,7 +1454,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
 
             /* Push instance data */
             ++cmd->texture.instance_count;
-            struct dx11_texture_instance *instance = dx11_buffer_push(plan->buffers.texture.instance_buffer, sizeof(struct dx11_texture_instance));
+            struct dx11_texture_instance *instance = dx11_buffer_push(plan->cmd_buffers.texture.instance_buffer, sizeof(struct dx11_texture_instance));
             instance->xf = params.texture.xf;
             instance->uv0 = params.texture.clip.p0;
             instance->uv1 = params.texture.clip.p1;
@@ -1490,7 +1475,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
                 /* TODO: Better count method */
                 cmd = arena_push(&plan->cpu_cmds_arena, struct dx11_cmd);
                 cmd->kind = params.kind;
-                cmd->grid.instance_offset = (plan->buffers.grid.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_grid_instance));
+                cmd->grid.instance_offset = (plan->cmd_buffers.grid.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_grid_instance));
                 if (plan->cpu_last_cmd) {
                     plan->cpu_last_cmd->next = cmd;
                 } else {
@@ -1501,7 +1486,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
 
             /* Push instance data */
             ++cmd->grid.instance_count;
-            struct dx11_grid_instance *instance = dx11_buffer_push(plan->buffers.grid.instance_buffer, sizeof(struct dx11_grid_instance));
+            struct dx11_grid_instance *instance = dx11_buffer_push(plan->cmd_buffers.grid.instance_buffer, sizeof(struct dx11_grid_instance));
             instance->xf = params.grid.xf;
             instance->line_thickness = params.grid.line_thickness;
             instance->line_spacing = params.grid.line_spacing;
@@ -1517,7 +1502,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
         {
             struct dx11_cmd *cmd = arena_push(&plan->cpu_cmds_arena, struct dx11_cmd);
             cmd->kind = params.kind;
-            cmd->test.instance_offset = (plan->buffers.test.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_test_instance));
+            cmd->test.instance_offset = (plan->cmd_buffers.test.instance_buffer->cpu_buffer_arena.pos / sizeof(struct dx11_test_instance));
             if (plan->cpu_last_cmd) {
                 plan->cpu_last_cmd->next = cmd;
             } else {
@@ -1527,7 +1512,7 @@ void gpu_push_cmd(struct gpu_handle gpu_plan, struct gpu_cmd_params params)
 
             /* Push instance data */
             ++cmd->test.instance_count;
-            struct dx11_test_instance *instance = dx11_buffer_push(plan->buffers.test.instance_buffer, sizeof(struct dx11_test_instance));
+            struct dx11_test_instance *instance = dx11_buffer_push(plan->cmd_buffers.test.instance_buffer, sizeof(struct dx11_test_instance));
             instance->xf = params.test.xf;
         } break;
     }
@@ -1551,43 +1536,17 @@ void gpu_submit_plan(struct gpu_handle gpu_plan)
     arena_reset(&plan->cpu_cmds_arena);
 
     /* Submit mesh buffers */
-    dx11_buffer_submit(plan->buffers.mesh.vertex_buffer);
-    dx11_buffer_submit(plan->buffers.mesh.index_buffer);
+    dx11_buffer_submit(plan->cmd_buffers.mesh.vertex_buffer);
+    dx11_buffer_submit(plan->cmd_buffers.mesh.index_buffer);
 
     /* Submit texture buffers */
-    dx11_buffer_submit(plan->buffers.texture.instance_buffer);
+    dx11_buffer_submit(plan->cmd_buffers.texture.instance_buffer);
 
     /* Submit grid buffers */
-    dx11_buffer_submit(plan->buffers.grid.instance_buffer);
+    dx11_buffer_submit(plan->cmd_buffers.grid.instance_buffer);
 
     /* Submit test buffers */
-    dx11_buffer_submit(plan->buffers.test.instance_buffer);
-}
-
-/* ========================== *
- * Dispatch state
- * ========================== */
-
-struct gpu_handle gpu_dispatch_state_alloc(void)
-{
-    __prof;
-    struct dx11_dispatch_state *state = NULL;
-    {
-        struct sys_lock lock = sys_mutex_lock_e(&G.dispatch_states_mutex);
-        if (G.first_free_dispatch_state) {
-            state = G.first_free_dispatch_state;
-            G.first_free_dispatch_state = state->next_free;
-        } else {
-            state = arena_push_no_zero(&G.dispatch_states_arena, struct dx11_dispatch_state);
-        }
-        sys_mutex_unlock(&lock);
-    }
-    MEMZERO_STRUCT(state);
-    state->header.kind = DX11_HANDLE_KIND_DISPATCH_STATE;
-
-    struct gpu_handle res = ZI;
-    res.v = (u64)state;
-    return res;
+    dx11_buffer_submit(plan->cmd_buffers.test.instance_buffer);
 }
 
 /* ========================== *
@@ -1661,12 +1620,11 @@ INTERNAL void dx11_unbind(u32 flags)
 }
 
 /* TODO: Lock resources during dispatch */
-void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_params params)
+void gpu_dispatch(struct gpu_dispatch_params params)
 {
     __prof;
     __profscope_dx11(G.profiling_ctx, Dispatch, RGB32_F(0.5, 0.2, 0.2));
     struct sprite_scope *sprite_scope = sprite_scope_begin();
-    struct dx11_dispatch_state *state = (struct dx11_dispatch_state *)gpu_dispatch_state.v;
     struct dx11_plan *plan = (struct dx11_plan *)params.plan.v;
 
     struct rect viewport = params.draw_target_viewport;
@@ -1682,10 +1640,9 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
     ID3D11DeviceContext_RSSetViewports(G.devcon, 1, &d3d11_viewport);
 
     struct dx11_texture *final_tex = (struct dx11_texture *)params.draw_target.v;
-    struct v2i32 final_tex_size = final_tex->size;
 
     /* Allocate constant buffer */
-    struct dx11_buffer *constant_buffer = state->constant_buffer;
+    struct dx11_buffer *constant_buffer = plan->constant_buffer;
     if (!constant_buffer) {
         const D3D11_BUFFER_DESC desc = {
             .Usage = D3D11_USAGE_DYNAMIC,
@@ -1693,17 +1650,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
             .CPUAccessFlags = D3D11_CPU_ACCESS_WRITE
         };
         constant_buffer = dx11_buffer_alloc(desc, NULL);
-        state->constant_buffer = constant_buffer;
-    }
-
-    /* Allocate / resize albedo */
-    struct dx11_texture *albedo_tex = state->albedo;
-    if (!albedo_tex || !v2i32_eq(albedo_tex->size, final_tex->size)) {
-        if (albedo_tex) {
-            dx11_texture_release(albedo_tex);
-        }
-        albedo_tex = dx11_texture_alloc(DXGI_FORMAT_R8G8B8A8_UNORM, D3D11_BIND_SHADER_RESOURCE | D3D11_BIND_RENDER_TARGET, final_tex_size, NULL);
-        state->albedo = albedo_tex;
+        plan->constant_buffer = constant_buffer;
     }
 
     /* Regular pass */
@@ -1727,8 +1674,8 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
                     __profscope_dx11(G.profiling_ctx, Draw mesh, RGB32_F(0.5, 0.2, 0.2));
                     struct dx11_shader *shader = &G.shaders[DX11_SHADER_KIND_MESH];
                     if (shader->valid) {
-                        struct dx11_buffer *vertex_buffer = plan->buffers.mesh.vertex_buffer;
-                        struct dx11_buffer *index_buffer = plan->buffers.mesh.index_buffer;
+                        struct dx11_buffer *vertex_buffer = plan->cmd_buffers.mesh.vertex_buffer;
+                        struct dx11_buffer *index_buffer = plan->cmd_buffers.mesh.index_buffer;
 
                         u32 vertex_offset = cmd->mesh.vertex_offset;
                         u32 index_offset = cmd->mesh.index_offset;
@@ -1786,7 +1733,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
                         }
 
                         if (texture && texture->srv) {
-                            struct dx11_buffer *instance_buffer = plan->buffers.texture.instance_buffer;
+                            struct dx11_buffer *instance_buffer = plan->cmd_buffers.texture.instance_buffer;
                             u32 instance_offset = cmd->texture.instance_offset;
                             u32 instance_count = cmd->texture.instance_count;
 
@@ -1835,7 +1782,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
                     __profscope_dx11(G.profiling_ctx, Draw grid, RGB32_F(0.2, 0.2, 0.5));
                     struct dx11_shader *shader = &G.shaders[DX11_SHADER_KIND_GRID];
                     if (shader->valid) {
-                        struct dx11_buffer *instance_buffer = plan->buffers.grid.instance_buffer;
+                        struct dx11_buffer *instance_buffer = plan->cmd_buffers.grid.instance_buffer;
                         u32 instance_offset = cmd->grid.instance_offset;
                         u32 instance_count = cmd->grid.instance_count;
 
@@ -1883,7 +1830,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
                     __profscope_dx11(G.profiling_ctx, Test, RGB32_F(1, 0.2, 1));
                     struct dx11_shader *shader = &G.shaders[DX11_SHADER_KIND_TEST];
                     if (shader->valid) {
-                        struct dx11_buffer *instance_buffer = plan->buffers.test.instance_buffer;
+                        struct dx11_buffer *instance_buffer = plan->cmd_buffers.test.instance_buffer;
                         u32 instance_offset = cmd->test.instance_offset;
                         u32 instance_count = cmd->test.instance_count;
 
@@ -2035,7 +1982,7 @@ INTERNAL void present_blit(struct dx11_texture *dst, struct dx11_texture *src, s
         params.draw_target = dst_texture_handle;
         params.draw_target_viewport = RECT_FROM_V2(V2(0, 0), V2(dst->size.x, dst->size.y));
         params.draw_target_view = XFORM_IDENT;
-        gpu_dispatch(G.present_blit_dispatch_state, params);
+        gpu_dispatch(params);
     }
 }
 
diff --git a/src/gpu_dx12.c b/src/gpu_dx12.c
index 8cc58ed9..779402b6 100644
--- a/src/gpu_dx12.c
+++ b/src/gpu_dx12.c
@@ -80,11 +80,11 @@ struct pipeline_error {
     struct string msg;
 };
 
-struct dx12_descriptor {
-    struct dx12_cpu_descriptor_heap *heap;
+struct descriptor {
+    struct cpu_descriptor_heap *heap;
     D3D12_CPU_DESCRIPTOR_HANDLE handle;
 
-    struct dx12_descriptor *next_free;
+    struct descriptor *next_free;
 };
 
 struct dx12_resource {
@@ -96,10 +96,10 @@ struct dx12_resource {
     D3D12_CPU_DESCRIPTOR_HANDLE uav_handle;
     D3D12_CPU_DESCRIPTOR_HANDLE rtv_handle;
 #else
-    struct dx12_descriptor *cbv_descriptor;
-    struct dx12_descriptor *srv_descriptor;
-    struct dx12_descriptor *uav_descriptor;
-    struct dx12_descriptor *rtv_descriptor;
+    struct descriptor *cbv_descriptor;
+    struct descriptor *srv_descriptor;
+    struct descriptor *uav_descriptor;
+    struct descriptor *rtv_descriptor;
 #endif
 
     D3D12_GPU_VIRTUAL_ADDRESS gpu_address;  /* NOTE: 0 for textures */
@@ -107,7 +107,7 @@ struct dx12_resource {
     struct dx12_resource *next_free;
 };
 
-struct dx12_cpu_descriptor_heap {
+struct cpu_descriptor_heap {
     enum D3D12_DESCRIPTOR_HEAP_TYPE type;
     struct arena arena;
     struct sys_mutex mutex;
@@ -116,13 +116,13 @@ struct dx12_cpu_descriptor_heap {
     u32 num_descriptors_reserved;
     u32 num_descriptors_capacity;
 
-    struct dx12_descriptor *first_free_descriptor;
+    struct descriptor *first_free_descriptor;
 
     ID3D12DescriptorHeap *heap;
     struct D3D12_CPU_DESCRIPTOR_HANDLE handle;
 };
 
-struct dx12_gpu_descriptor_heap {
+struct gpu_descriptor_heap {
     D3D12_DESCRIPTOR_HEAP_TYPE type;
     ID3D12DescriptorHeap *heap;
     D3D12_CPU_DESCRIPTOR_HANDLE cpu_handle;
@@ -132,26 +132,25 @@ struct dx12_gpu_descriptor_heap {
     ID3D12Fence *free_fence;
     u64 free_fence_value;
 
-    struct dx12_gpu_descriptor_heap *prev_free;
-    struct dx12_gpu_descriptor_heap *next_free;
+    struct gpu_descriptor_heap *prev_free;
+    struct gpu_descriptor_heap *next_free;
 };
 
-enum dx12_handle_kind {
+enum handle_kind {
     DX12_HANDLE_KIND_NONE,
     DX12_HANDLE_KIND_RESOURCE,
     DX12_HANDLE_KIND_PLAN,
-    DX12_HANDLE_KIND_DISPATCH_STATE,
 
     NUM_DX12_HANDLE_KINDS
 };
 
-struct dx12_handle_entry {
-    enum dx12_handle_kind kind;
+struct handle_entry {
+    enum handle_kind kind;
     u64 gen;
     u64 idx;
     void *data;
 
-    struct dx12_handle_entry *next_free;
+    struct handle_entry *next_free;
 };
 
 /* ========================== *
@@ -162,14 +161,14 @@ GLOBAL struct {
     /* Handles pool */
     struct sys_mutex handle_entries_mutex;
     struct arena handle_entries_arena;
-    struct dx12_handle_entry *first_free_handle_entry;
+    struct handle_entry *first_free_handle_entry;
     u64 num_handle_entries_reserved;
 
     /* Descriptor heaps pool */
     struct sys_mutex gpu_descriptor_heaps_mutex;
     struct arena gpu_descriptor_heaps_arena;
-    struct dx12_gpu_descriptor_heap *first_free_gpu_descriptor_heap;
-    struct dx12_gpu_descriptor_heap *last_free_gpu_descriptor_heap;
+    struct gpu_descriptor_heap *first_free_gpu_descriptor_heap;
+    struct gpu_descriptor_heap *last_free_gpu_descriptor_heap;
 
     /* Resources pool */
     struct sys_mutex resources_mutex;
@@ -204,8 +203,8 @@ GLOBAL struct {
     u32 desc_counts[D3D12_DESCRIPTOR_HEAP_TYPE_NUM_TYPES];
 
     /* Global descriptor heaps */
-    struct dx12_cpu_descriptor_heap *cbv_srv_uav_heap;
-    struct dx12_cpu_descriptor_heap *rtv_heap;
+    struct cpu_descriptor_heap *cbv_srv_uav_heap;
+    struct cpu_descriptor_heap *rtv_heap;
 
     /* Command queues */
     /* TODO: Add optional mode to route everything to direct queue */
@@ -233,7 +232,7 @@ GLOBAL struct {
  * ========================== */
 
 INTERNAL APP_EXIT_CALLBACK_FUNC_DEF(gpu_shutdown);
-INTERNAL struct dx12_cpu_descriptor_heap *dx12_cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
+INTERNAL struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type);
 INTERNAL void dx12_init_device(void);
 INTERNAL void dx12_init_objects(void);
 INTERNAL void dx12_init_swapchain(struct sys_window *window);
@@ -356,11 +355,11 @@ INTERNAL APP_EXIT_CALLBACK_FUNC_DEF(gpu_shutdown)
 
 INTERNAL void dx12_resource_release(struct dx12_resource *t);
 
-INTERNAL struct gpu_handle handle_alloc(enum dx12_handle_kind kind, void *data)
+INTERNAL struct gpu_handle handle_alloc(enum handle_kind kind, void *data)
 {
     u64 old_gen = 0;
     u64 idx = 0;
-    struct dx12_handle_entry *entry = NULL;
+    struct handle_entry *entry = NULL;
     {
         struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex);
         if (G.first_free_handle_entry) {
@@ -369,7 +368,7 @@ INTERNAL struct gpu_handle handle_alloc(enum dx12_handle_kind kind, void *data)
             old_gen = entry->gen;
             idx = entry->idx;
         } else {
-            entry = arena_push_no_zero(&G.handle_entries_arena, struct dx12_handle_entry);
+            entry = arena_push_no_zero(&G.handle_entries_arena, struct handle_entry);
             idx = G.num_handle_entries_reserved++;
         }
         sys_mutex_unlock(&lock);
@@ -386,12 +385,12 @@ INTERNAL struct gpu_handle handle_alloc(enum dx12_handle_kind kind, void *data)
     return res;
 }
 
-INTERNAL struct dx12_handle_entry *handle_get_entry(struct gpu_handle handle, struct sys_lock *lock)
+INTERNAL struct handle_entry *handle_get_entry(struct gpu_handle handle, struct sys_lock *lock)
 {
     sys_assert_locked_e_or_s(lock, &G.handle_entries_mutex);
-    struct dx12_handle_entry *res = NULL;
+    struct handle_entry *res = NULL;
     if (handle.idx > 0 && handle.idx < G.num_handle_entries_reserved) {
-        struct dx12_handle_entry *tmp = &((struct dx12_handle_entry *)G.handle_entries_arena.base)[handle.idx];
+        struct handle_entry *tmp = &((struct handle_entry *)G.handle_entries_arena.base)[handle.idx];
         if (tmp->gen == handle.gen) {
             res = tmp;
         }
@@ -399,12 +398,12 @@ INTERNAL struct dx12_handle_entry *handle_get_entry(struct gpu_handle handle, st
     return res;
 }
 
-INTERNAL void *handle_get_data(struct gpu_handle handle, enum dx12_handle_kind kind)
+INTERNAL void *handle_get_data(struct gpu_handle handle, enum handle_kind kind)
 {
     void *data = NULL;
     struct sys_lock lock = sys_mutex_lock_s(&G.handle_entries_mutex);
     {
-        struct dx12_handle_entry *entry = handle_get_entry(handle, &lock);
+        struct handle_entry *entry = handle_get_entry(handle, &lock);
         data = entry->data;
 #if RTC
         /* Handle should match expected kind */
@@ -420,13 +419,13 @@ INTERNAL void *handle_get_data(struct gpu_handle handle, enum dx12_handle_kind k
  * to ensure freed textures aren't being used in pending command lists. */
 void gpu_release(struct gpu_handle handle)
 {
-    enum dx12_handle_kind kind = 0;
+    enum handle_kind kind = 0;
     void *data = NULL;
 
     /* Release handle entry */
     struct sys_lock lock = sys_mutex_lock_e(&G.handle_entries_mutex);
     {
-        struct dx12_handle_entry *entry = handle_get_entry(handle, &lock);
+        struct handle_entry *entry = handle_get_entry(handle, &lock);
         if (entry) {
             kind = entry->kind;
             data = entry->data;
@@ -589,8 +588,8 @@ INTERNAL void dx12_init_objects(void)
     G.desc_counts[D3D12_DESCRIPTOR_HEAP_TYPE_RTV] = DX12_NUM_RTV_DESCRIPTORS;
 
     /* Create global descriptor heaps */
-    G.cbv_srv_uav_heap = dx12_cpu_descriptor_heap_alloc(D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);
-    G.rtv_heap = dx12_cpu_descriptor_heap_alloc(D3D12_DESCRIPTOR_HEAP_TYPE_RTV);
+    G.cbv_srv_uav_heap = cpu_descriptor_heap_alloc(D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);
+    G.rtv_heap = cpu_descriptor_heap_alloc(D3D12_DESCRIPTOR_HEAP_TYPE_RTV);
 
     /* Create direct command queue */
     {
@@ -1221,12 +1220,12 @@ INTERNAL void pipeline_release(struct pipeline *pipeline)
  * CPU descriptor heap
  * ========================== */
 
-INTERNAL struct dx12_cpu_descriptor_heap *dx12_cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type)
+INTERNAL struct cpu_descriptor_heap *cpu_descriptor_heap_alloc(enum D3D12_DESCRIPTOR_HEAP_TYPE type)
 {
-    struct dx12_cpu_descriptor_heap *dh = NULL;
+    struct cpu_descriptor_heap *dh = NULL;
     {
         struct arena arena = arena_alloc(MEGABYTE(64));
-        dh = arena_push(&arena, struct dx12_cpu_descriptor_heap);
+        dh = arena_push(&arena, struct cpu_descriptor_heap);
         dh->arena = arena;
     }
     dh->mutex = sys_mutex_alloc();
@@ -1257,7 +1256,7 @@ INTERNAL struct dx12_cpu_descriptor_heap *dx12_cpu_descriptor_heap_alloc(enum D3
 }
 
 #if 0
-INTERNAL void dx12_cpu_descriptor_heap_release(struct dx12_cpu_descriptor_heap *dh)
+INTERNAL void cpu_descriptor_heap_release(struct cpu_descriptor_heap *dh)
 {
     /* TODO */
     (UNUSED)dh;
@@ -1268,9 +1267,9 @@ INTERNAL void dx12_cpu_descriptor_heap_release(struct dx12_cpu_descriptor_heap *
  * Descriptor
  * ========================== */
 
-INTERNAL struct dx12_descriptor *dx12_descriptor_alloc(struct dx12_cpu_descriptor_heap *dh)
+INTERNAL struct descriptor *descriptor_alloc(struct cpu_descriptor_heap *dh)
 {
-    struct dx12_descriptor *d = NULL;
+    struct descriptor *d = NULL;
     D3D12_CPU_DESCRIPTOR_HANDLE handle = ZI;
     {
         struct sys_lock lock = sys_mutex_lock_e(&dh->mutex);
@@ -1282,7 +1281,7 @@ INTERNAL struct dx12_descriptor *dx12_descriptor_alloc(struct dx12_cpu_descripto
                 sys_panic(LIT("Max descriptors reached in heap"));
             }
 
-            d = arena_push_no_zero(&dh->arena, struct dx12_descriptor);
+            d = arena_push_no_zero(&dh->arena, struct descriptor);
             handle.ptr = dh->handle.ptr + (dh->num_descriptors_reserved * dh->descriptor_size);
             ++dh->num_descriptors_reserved;
         }
@@ -1298,12 +1297,12 @@ INTERNAL struct dx12_descriptor *dx12_descriptor_alloc(struct dx12_cpu_descripto
  * GPU (shader visible) descriptor heap
  * ========================== */
 
-INTERNAL struct dx12_gpu_descriptor_heap *dx12_gpu_descriptor_heap_alloc(struct dx12_cpu_descriptor_heap *dh_cpu)
+INTERNAL struct gpu_descriptor_heap *gpu_descriptor_heap_alloc(struct cpu_descriptor_heap *dh_cpu)
 {
     ASSERT(dh_cpu->type == D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);  /* Src heap must have expected type */
 
     /* Allocate GPU heap */
-    struct dx12_gpu_descriptor_heap *dh_gpu = NULL;
+    struct gpu_descriptor_heap *dh_gpu = NULL;
     ID3D12DescriptorHeap *heap = NULL;
     D3D12_CPU_DESCRIPTOR_HANDLE cpu_handle = ZI;
     D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle = ZI;
@@ -1313,7 +1312,7 @@ INTERNAL struct dx12_gpu_descriptor_heap *dx12_gpu_descriptor_heap_alloc(struct
         struct sys_lock lock = sys_mutex_lock_e(&G.gpu_descriptor_heaps_mutex);
         /* Find first free & ready heap for reuse */
         /* FIXME: Rather than storing fence per heap, store & increment fence per queue and check against it */
-        for (struct dx12_gpu_descriptor_heap *tmp = G.first_free_gpu_descriptor_heap; tmp; tmp = tmp->next_free) {
+        for (struct gpu_descriptor_heap *tmp = G.first_free_gpu_descriptor_heap; tmp; tmp = tmp->next_free) {
             if (ID3D12Fence_GetCompletedValue(tmp->free_fence) >= tmp->free_fence_value) {
                 dh_gpu = tmp;
                 break;
@@ -1328,8 +1327,8 @@ INTERNAL struct dx12_gpu_descriptor_heap *dx12_gpu_descriptor_heap_alloc(struct
             free_fence = dh_gpu->free_fence;
             free_fence_value = dh_gpu->free_fence_value;
             /* Remove from free list */
-            struct dx12_gpu_descriptor_heap *prev = dh_gpu->prev_free;
-            struct dx12_gpu_descriptor_heap *next = dh_gpu->next_free;
+            struct gpu_descriptor_heap *prev = dh_gpu->prev_free;
+            struct gpu_descriptor_heap *next = dh_gpu->next_free;
             if (prev) {
                 prev->next_free = next;
             } else {
@@ -1342,7 +1341,7 @@ INTERNAL struct dx12_gpu_descriptor_heap *dx12_gpu_descriptor_heap_alloc(struct
             }
         } else {
             /* No available heap available for reuse, allocate new */
-            dh_gpu = arena_push_no_zero(&G.gpu_descriptor_heaps_arena, struct dx12_gpu_descriptor_heap);
+            dh_gpu = arena_push_no_zero(&G.gpu_descriptor_heaps_arena, struct gpu_descriptor_heap);
         }
         sys_mutex_unlock(&lock);
     }
@@ -1379,7 +1378,7 @@ INTERNAL struct dx12_gpu_descriptor_heap *dx12_gpu_descriptor_heap_alloc(struct
     return dh_gpu;
 }
 
-INTERNAL void dx12_gpu_descriptor_heap_release(struct dx12_gpu_descriptor_heap *dh, ID3D12CommandQueue *cq)
+INTERNAL void gpu_descriptor_heap_release(struct gpu_descriptor_heap *dh, ID3D12CommandQueue *cq)
 {
     /* Queue fence signal */
     ++dh->free_fence_value;
@@ -1401,18 +1400,46 @@ INTERNAL void dx12_gpu_descriptor_heap_release(struct dx12_gpu_descriptor_heap *
  * Plan
  * ========================== */
 
-struct dx12_plan {
-    struct dx12_plan *next_free;
+ /* TODO: Move command list out of plan struct */
+struct plan {
+    struct arena arena;
+    ID3D12CommandAllocator *ca_direct;
+    ID3D12GraphicsCommandList *cl_direct;
+
+    struct plan *next_free;
 };
 
-INTERNAL struct dx12_plan *dx12_plan_alloc(void)
+INTERNAL struct plan *plan_alloc(void)
 {
-    return NULL;
+    HRESULT hr = 0;
+    struct plan *plan = NULL;
+    {
+        struct arena arena = arena_alloc(MEGABYTE(64));
+        plan = arena_push(&arena, struct plan);
+        plan->arena = arena;
+    }
+
+    hr = ID3D12Device_CreateCommandAllocator(G.device, D3D12_COMMAND_LIST_TYPE_DIRECT, &IID_ID3D12CommandAllocator, (void **)&plan->ca_direct);
+    if (FAILED(hr)) {
+        sys_panic(LIT("Failed to create command allocator"));
+    }
+
+    hr = ID3D12Device_CreateCommandList(G.device, 0, D3D12_COMMAND_LIST_TYPE_DIRECT, plan->ca_direct, NULL, &IID_ID3D12GraphicsCommandList, (void **)&plan->cl_direct);
+    if (FAILED(hr)) {
+        sys_panic(LIT("Failed to create command list"));
+    }
+
+    hr = ID3D12GraphicsCommandList_Close(plan->cl_direct);
+    if (FAILED(hr)) {
+        sys_panic(LIT("Failed to close command list during initialization"));
+    }
+
+    return plan;
 }
 
 struct gpu_handle gpu_plan_alloc(void)
 {
-    struct dx12_plan *plan = dx12_plan_alloc();
+    struct plan *plan = plan_alloc();
     return handle_alloc(DX12_HANDLE_KIND_PLAN, plan);
 }
 
@@ -1467,7 +1494,7 @@ INTERNAL struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_pr
     }
 
     if (view_flags & DX12_RESOURCE_VIEW_FLAG_CBV) {
-        r->cbv_descriptor = dx12_descriptor_alloc(G.cbv_srv_uav_heap);
+        r->cbv_descriptor = descriptor_alloc(G.cbv_srv_uav_heap);
         D3D12_CONSTANT_BUFFER_VIEW_DESC cbv_desc = ZI;
         cbv_desc.BufferLocation = r->gpu_address;
         //cbv_desc.SizeInBytes = desc.ByteWidth;
@@ -1476,15 +1503,15 @@ INTERNAL struct dx12_resource *dx12_resource_alloc(D3D12_HEAP_PROPERTIES heap_pr
         ID3D12Device_CreateConstantBufferView(G.device, &cbv_desc, r->cbv_descriptor->handle);
     }
     if (view_flags & DX12_RESOURCE_VIEW_FLAG_SRV) {
-        r->srv_descriptor = dx12_descriptor_alloc(G.cbv_srv_uav_heap);
+        r->srv_descriptor = descriptor_alloc(G.cbv_srv_uav_heap);
         ID3D12Device_CreateShaderResourceView(G.device, r->resource, NULL, r->srv_descriptor->handle);
     }
     if (view_flags & DX12_RESOURCE_VIEW_FLAG_UAV) {
-        r->uav_descriptor = dx12_descriptor_alloc(G.cbv_srv_uav_heap);
+        r->uav_descriptor = descriptor_alloc(G.cbv_srv_uav_heap);
         ID3D12Device_CreateUnorderedAccessView(G.device, r->resource, NULL, NULL, r->uav_descriptor->handle);
     }
     if (view_flags & DX12_RESOURCE_VIEW_FLAG_RTV) {
-        r->rtv_descriptor = dx12_descriptor_alloc(G.rtv_heap);
+        r->rtv_descriptor = descriptor_alloc(G.rtv_heap);
         ID3D12Device_CreateRenderTargetView(G.device, r->resource, NULL, r->rtv_descriptor->handle);
     }
 
@@ -1583,48 +1610,7 @@ struct v2i32 gpu_texture_get_size(struct gpu_handle resource)
  * Dispatch
  * ========================== */
 
-/* TODO: Move command list off of dispatch state */
-struct dx12_dispatch_state {
-    struct arena arena;
-    ID3D12CommandAllocator *ca_direct;
-    ID3D12GraphicsCommandList *cl_direct;
-};
-
-INTERNAL struct dx12_dispatch_state *dx12_dispatch_state_alloc(void)
-{
-    HRESULT hr = 0;
-    struct dx12_dispatch_state *ds = NULL;
-    {
-        struct arena arena = arena_alloc(MEGABYTE(64));
-        ds = arena_push(&arena, struct dx12_dispatch_state);
-        ds->arena = arena;
-    }
-
-    hr = ID3D12Device_CreateCommandAllocator(G.device, D3D12_COMMAND_LIST_TYPE_DIRECT, &IID_ID3D12CommandAllocator, (void **)&ds->ca_direct);
-    if (FAILED(hr)) {
-        sys_panic(LIT("Failed to create command allocator"));
-    }
-
-    hr = ID3D12Device_CreateCommandList(G.device, 0, D3D12_COMMAND_LIST_TYPE_DIRECT, ds->ca_direct, NULL, &IID_ID3D12GraphicsCommandList, (void **)&ds->cl_direct);
-    if (FAILED(hr)) {
-        sys_panic(LIT("Failed to create command list"));
-    }
-
-    hr = ID3D12GraphicsCommandList_Close(ds->cl_direct);
-    if (FAILED(hr)) {
-        sys_panic(LIT("Failed to close command list during initialization"));
-    }
-
-    return ds;
-}
-
-struct gpu_handle gpu_dispatch_state_alloc(void)
-{
-    struct dx12_dispatch_state *ds = dx12_dispatch_state_alloc();
-    return handle_alloc(DX12_HANDLE_KIND_DISPATCH_STATE, ds);
-}
-
-void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_params params)
+void gpu_dispatch(struct gpu_dispatch_params params)
 {
     HRESULT hr = 0;
 
@@ -1646,13 +1632,12 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
     d3d12_scissor.right = viewport.x + viewport.width;
     d3d12_scissor.bottom = viewport.y + viewport.height;
 
-    struct dx12_dispatch_state *dispatch_state = handle_get_data(gpu_dispatch_state, DX12_HANDLE_KIND_DISPATCH_STATE);
-    struct dx12_plan *plan = handle_get_data(params.plan, DX12_HANDLE_KIND_PLAN);
+    struct plan *plan = handle_get_data(params.plan, DX12_HANDLE_KIND_PLAN);
     struct dx12_resource *target = handle_get_data(params.draw_target, DX12_HANDLE_KIND_RESOURCE);
 
     ID3D12CommandQueue *cq = G.cq_direct;
-    ID3D12CommandAllocator *ca = dispatch_state->ca_direct;
-    ID3D12GraphicsCommandList *cl = dispatch_state->cl_direct;
+    ID3D12CommandAllocator *ca = plan->ca_direct;
+    ID3D12GraphicsCommandList *cl = plan->cl_direct;
 
     /* FIXME: Use fence to ensure command allocator has finished execution on GPU before resetting */
     hr = ID3D12CommandAllocator_Reset(ca);
@@ -1666,7 +1651,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
     }
 
     /* Create temporary srv heap */
-    struct dx12_gpu_descriptor_heap *temp_descriptor_heap = dx12_gpu_descriptor_heap_alloc(G.cbv_srv_uav_heap);
+    struct gpu_descriptor_heap *temp_descriptor_heap = gpu_descriptor_heap_alloc(G.cbv_srv_uav_heap);
 
     /* Material pass */
     {
@@ -1714,7 +1699,7 @@ void gpu_dispatch(struct gpu_handle gpu_dispatch_state, struct gpu_dispatch_para
         sys_panic(LIT("Failed to close command list before execution"));
     }
 
-    dx12_gpu_descriptor_heap_release(temp_descriptor_heap, cq);
+    gpu_descriptor_heap_release(temp_descriptor_heap, cq);
 
 #if 0
     __prof;
diff --git a/src/user.c b/src/user.c
index 2fb87150..14e7a651 100644
--- a/src/user.c
+++ b/src/user.c
@@ -75,10 +75,6 @@ GLOBAL struct {
 
     struct gpu_handle world_gpu_plan;
     struct gpu_handle ui_gpu_plan;
-    struct gpu_handle backbuffer_gpu_plan;
-
-    struct gpu_handle user_dispatch_state;
-    struct gpu_handle backbuffer_dispatch_state;
 
     struct xform world_to_user_xf;
 
@@ -259,9 +255,6 @@ struct user_startup_receipt user_startup(struct work_startup_receipt *work_sr,
     G.world_to_user_xf = XFORM_IDENT;
     G.world_gpu_plan = gpu_plan_alloc();
     G.ui_gpu_plan = gpu_plan_alloc();
-    G.backbuffer_gpu_plan = gpu_plan_alloc();
-    G.user_dispatch_state = gpu_dispatch_state_alloc();
-    G.backbuffer_dispatch_state = gpu_dispatch_state_alloc();
 
     G.console_logs_mutex = sys_mutex_alloc();
     G.console_logs_arena = arena_alloc(GIGABYTE(64));
@@ -2082,7 +2075,6 @@ INTERNAL void user_update(void)
         /* Send plans to GPU */
         gpu_submit_plan(G.world_gpu_plan);
         gpu_submit_plan(G.ui_gpu_plan);
-        gpu_submit_plan(G.backbuffer_gpu_plan);
 
         /* Clear textures */
         gpu_texture_clear(G.user_texture, 0);
@@ -2094,7 +2086,7 @@ INTERNAL void user_update(void)
             params.draw_target = G.user_texture;
             params.draw_target_viewport = user_viewport;
             params.draw_target_view = G.world_to_user_xf;
-            gpu_dispatch(G.user_dispatch_state, params);
+            gpu_dispatch(params);
         }
 
         /* Render ui to user texture */
@@ -2104,7 +2096,7 @@ INTERNAL void user_update(void)
             params.draw_target = G.user_texture;
             params.draw_target_viewport = user_viewport;
             params.draw_target_view = XFORM_IDENT;
-            gpu_dispatch(G.user_dispatch_state, params);
+            gpu_dispatch(params);
         }
 
         /* Present user texture */