From 1144eef5b370ec5b8ad36f388922d7aaf20fd76d Mon Sep 17 00:00:00 2001
From: jacob <jacob@cagori.com>
Date: Sat, 22 Nov 2025 16:12:44 -0600
Subject: [PATCH] enhanced barrier testing

---
 src/gpu/gpu_dx12/gpu_dx12.c | 56 ++++++++++++++++++++++++++++++++-----
 src/gpu/gpu_dx12/gpu_dx12.h |  2 +-
 2 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/src/gpu/gpu_dx12/gpu_dx12.c b/src/gpu/gpu_dx12/gpu_dx12.c
index 8185c357..0651ef27 100644
--- a/src/gpu/gpu_dx12/gpu_dx12.c
+++ b/src/gpu/gpu_dx12/gpu_dx12.c
@@ -582,7 +582,7 @@ GPU_D12_RawCommandList *GPU_D12_PrepareRawCommandList(GPU_QueueKind queue_kind)
             Panic(Lit("Failed to create command allocator"));
         }
 
-        hr = ID3D12Device_CreateCommandList(g->device, 0, queue->desc.type, cl->ca, 0, &IID_ID3D12GraphicsCommandList, (void **)&cl->cl);
+        hr = ID3D12Device_CreateCommandList(g->device, 0, queue->desc.type, cl->ca, 0, &IID_ID3D12GraphicsCommandList7, (void **)&cl->cl);
         if (FAILED(hr))
         {
             Panic(Lit("Failed to create command list"));
@@ -1398,7 +1398,7 @@ void GPU_CommitCommandList(GPU_CommandListHandle cl_handle, GPU_QueueKind queue_
 
     /* Begin dx12 command list */
     GPU_D12_RawCommandList *dx12_cl = GPU_D12_PrepareRawCommandList(queue_kind);
-    ID3D12GraphicsCommandList *rcl = dx12_cl->cl;
+    ID3D12GraphicsCommandList7 *rcl = dx12_cl->cl;
 
     /* Pipeline state */
     b32 graphics_rootsig_set = 0;
@@ -1657,7 +1657,49 @@ void GPU_CommitCommandList(GPU_CommandListHandle cl_handle, GPU_QueueKind queue_
 
                 case GPU_D12_CmdKind_Access:
                 {
-                    /* TODO */
+                    /* FIXME: Batch */
+
+                    /* FIXME: Remove hardcode test */
+
+                    GPU_D12_Resource *resource = cmd->access.resource;
+
+                    D3D12_TEXTURE_BARRIER d3d_barrier = ZI;
+                    d3d_barrier.pResource = resource->d3d_resource;
+                    d3d_barrier.Subresources.IndexOrFirstMipLevel = 0xffffffff;
+
+
+                    switch (cmd->access.kind)
+                    {
+                        case GPU_AccessKind_RasterTarget:
+                        {
+                            d3d_barrier.SyncBefore = D3D12_BARRIER_SYNC_NONE;
+                            d3d_barrier.SyncAfter = D3D12_BARRIER_SYNC_RENDER_TARGET;
+                            d3d_barrier.AccessBefore = D3D12_BARRIER_ACCESS_NO_ACCESS;
+                            d3d_barrier.AccessAfter = D3D12_BARRIER_ACCESS_RENDER_TARGET;
+                            d3d_barrier.LayoutBefore = resource->texture_layout;
+                            d3d_barrier.LayoutAfter = D3D12_BARRIER_LAYOUT_RENDER_TARGET;
+                        } break;
+
+                        case GPU_AccessKind_Present:
+                        {
+                            d3d_barrier.SyncBefore = D3D12_BARRIER_SYNC_RENDER_TARGET;
+                            d3d_barrier.SyncAfter = D3D12_BARRIER_SYNC_NONE;
+                            d3d_barrier.AccessBefore = D3D12_BARRIER_ACCESS_RENDER_TARGET;
+                            d3d_barrier.AccessAfter = D3D12_BARRIER_ACCESS_NO_ACCESS;
+                            d3d_barrier.LayoutBefore = resource->texture_layout;
+                            d3d_barrier.LayoutAfter = D3D12_BARRIER_LAYOUT_PRESENT;
+                        } break;
+                    }
+
+                    D3D12_BARRIER_GROUP d3d_barrier_group = ZI;
+                    d3d_barrier_group.Type = D3D12_BARRIER_TYPE_TEXTURE;
+                    d3d_barrier_group.NumBarriers = 1;
+                    d3d_barrier_group.pTextureBarriers = &d3d_barrier;
+
+                    ID3D12GraphicsCommandList7_Barrier(rcl, 1, &d3d_barrier_group);
+
+                    resource->texture_layout = d3d_barrier.LayoutAfter;
+
                     cmd_idx += 1;
                 } break;
 
@@ -1897,10 +1939,10 @@ void GPU_CommitCommandList(GPU_CommandListHandle cl_handle, GPU_QueueKind queue_
                     GPU_D12_Resource *resource = descriptor->resource;
                     Assert(resource->texture_layout == D3D12_BARRIER_LAYOUT_RENDER_TARGET);
                     f32 clear_color[4] = ZI;
-                    clear_color[0] = resource->texture_desc.clear_color.x;
-                    clear_color[1] = resource->texture_desc.clear_color.y;
-                    clear_color[2] = resource->texture_desc.clear_color.z;
-                    clear_color[3] = resource->texture_desc.clear_color.w;
+                    clear_color[0] = cmd->clear_rtv.color.x;
+                    clear_color[1] = cmd->clear_rtv.color.y;
+                    clear_color[2] = cmd->clear_rtv.color.z;
+                    clear_color[3] = cmd->clear_rtv.color.w;
                     ID3D12GraphicsCommandList_ClearRenderTargetView(rcl, descriptor->handle, clear_color, 0, 0);
                     cmd_idx += 1;
                 } break;
diff --git a/src/gpu/gpu_dx12/gpu_dx12.h b/src/gpu/gpu_dx12/gpu_dx12.h
index bff52de5..1dab2579 100644
--- a/src/gpu/gpu_dx12/gpu_dx12.h
+++ b/src/gpu/gpu_dx12/gpu_dx12.h
@@ -164,7 +164,7 @@ Struct(GPU_D12_RawCommandList)
     u64 commit_fence_target;
 
     ID3D12CommandAllocator *ca;
-    ID3D12GraphicsCommandList *cl;
+    ID3D12GraphicsCommandList7 *cl;
 };
 
 ////////////////////////////////////////////////////////////