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101
src/gpu_dx12.c
101
src/gpu_dx12.c
@ -43,29 +43,29 @@
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# define DX12_SHADER_DEBUG 0
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#endif
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enum dx12_pipeline_desc_flags {
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DX12_PIPELINE_DESC_FLAG_NONE = 0,
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DX12_PIPELINE_DESC_FLAG_VS = (1 << 0),
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DX12_PIPELINE_DESC_FLAG_PS = (1 << 1)
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enum pipeline_desc_flags {
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PIPELINE_DESC_FLAG_NONE = 0,
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PIPELINE_DESC_FLAG_VS = (1 << 0),
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PIPELINE_DESC_FLAG_PS = (1 << 1)
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};
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struct dx12_pipeline_desc {
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struct pipeline_desc {
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char *shader;
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u32 flags;
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};
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struct dx12_pipeline {
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struct dx12_pipeline_desc desc;
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struct pipeline {
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struct pipeline_desc desc;
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ID3D12PipelineState *pso;
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};
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struct dx12_pipeline_result {
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struct dx12_pipeline pipeline;
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struct pipeline_result {
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struct pipeline pipeline;
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u64 errors_text_len;
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u8 errors_text[KILOBYTE(16)];
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};
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struct dx12_pipeline_error {
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struct pipeline_error {
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struct string msg;
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};
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@ -85,7 +85,7 @@ struct dx12_handle_entry {
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struct dx12_handle_entry *next_free;
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};
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struct dx12_texture {
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struct dx12_buffer {
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i32 _;
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};
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@ -172,7 +172,7 @@ INTERNAL APP_EXIT_CALLBACK_FUNC_DEF(gpu_shutdown)
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* Handle
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* ========================== */
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INTERNAL void dx12_texture_release(struct dx12_texture *t);
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INTERNAL void dx12_buffer_release(struct dx12_buffer *t);
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INTERNAL struct gpu_handle handle_alloc(enum dx12_handle_kind kind, void *data)
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{
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@ -246,7 +246,7 @@ void gpu_release(struct gpu_handle handle)
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case DX12_HANDLE_KIND_TEXTURE:
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{
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dx12_texture_release(data);
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dx12_buffer_release(data);
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} break;
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}
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}
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@ -528,12 +528,12 @@ INTERNAL void dx12_init_base(struct sys_window *window)
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/* ============= */
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/* Texture pipeline */
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PACK(struct dx12_texture_pipeline_uniform {
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PACK(struct dx12_buffer_pipeline_uniform {
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struct mat4x4 vp;
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u32 instance_offset;
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});
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PACK(struct dx12_texture_pipeline_instance {
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PACK(struct dx12_buffer_pipeline_instance {
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struct xform xf;
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struct v2 uv0;
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struct v2 uv1;
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@ -547,29 +547,29 @@ PACK(struct dx12_texture_pipeline_instance {
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/* ============= */
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/* Init pipelines */
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INTERNAL struct dx12_pipeline_result *pipeline_alloc_from_descs(struct arena *arena, u64 num_pipelines, struct dx12_pipeline_desc *descs);
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INTERNAL void dx12_pipeline_release(struct dx12_pipeline *pipeline);
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INTERNAL struct pipeline_result *pipeline_alloc_from_descs(struct arena *arena, u64 num_pipelines, struct pipeline_desc *descs);
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INTERNAL void pipeline_release(struct pipeline *pipeline);
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INTERNAL void dx12_init_pipelines(void)
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{
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__prof;
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struct arena_temp scratch = scratch_begin_no_conflict();
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struct dx12_pipeline_desc pipeline_descs[] = {
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struct pipeline_desc pipeline_descs[] = {
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/* Texture pipeline */
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{
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.shader = "shaders/texture.hlsl",
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.flags = DX12_PIPELINE_DESC_FLAG_VS |
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DX12_PIPELINE_DESC_FLAG_PS
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.flags = PIPELINE_DESC_FLAG_VS |
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PIPELINE_DESC_FLAG_PS
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}
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};
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struct dx12_pipeline_result *results = pipeline_alloc_from_descs(scratch.arena, ARRAY_COUNT(pipeline_descs), pipeline_descs);
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struct pipeline_result *results = pipeline_alloc_from_descs(scratch.arena, ARRAY_COUNT(pipeline_descs), pipeline_descs);
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for (u64 i = 0; i < ARRAY_COUNT(pipeline_descs); ++i) {
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struct dx12_pipeline_result *result = &results[i];
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struct pipeline_result *result = &results[i];
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if (result->errors_text_len > 0) {
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struct string msg = STRING(result->errors_text_len, result->errors_text);
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sys_panic(msg);
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dx12_pipeline_release(&result->pipeline);
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pipeline_release(&result->pipeline);
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} else {
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/* TODO */
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}
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@ -585,7 +585,7 @@ INTERNAL void dx12_init_pipelines(void)
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struct dx12_include_handler {
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ID3DInclude d3d_handler;
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ID3DIncludeVtbl vtbl;
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struct dx12_pipeline *pipeline;
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struct pipeline *pipeline;
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b32 has_open_resource;
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struct resource res;
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};
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@ -634,7 +634,7 @@ INTERNAL HRESULT dx12_include_close(ID3DInclude *d3d_handler, LPCVOID data)
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return S_OK;
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}
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INTERNAL struct dx12_include_handler dx12_include_handler_alloc(struct dx12_pipeline *pipeline)
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INTERNAL struct dx12_include_handler dx12_include_handler_alloc(struct pipeline *pipeline)
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{
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struct dx12_include_handler handler = ZI;
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handler.d3d_handler.lpVtbl = &handler.vtbl;
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@ -652,9 +652,6 @@ INTERNAL void dx12_include_handler_release(struct dx12_include_handler *handler)
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}
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}
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/* TODO: Compile shaders offline w/ dxc.
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* Will also allow for some hlsl language features like static_assert */
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enum shader_compile_task_kind {
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SHADER_COMPILE_TASK_KIND_VS,
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SHADER_COMPILE_TASK_KIND_PS
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@ -663,7 +660,7 @@ enum shader_compile_task_kind {
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struct shader_compile_task_arg {
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/* In */
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enum shader_compile_task_kind kind;
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struct dx12_pipeline *pipeline;
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struct pipeline *pipeline;
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struct resource *src_res;
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/* Out */
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@ -672,11 +669,12 @@ struct shader_compile_task_arg {
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ID3DBlob *error_blob;
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};
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/* TODO: Compile shaders offline w/ dxc for performance & language features like static_assert */
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INTERNAL WORK_TASK_FUNC_DEF(shader_compile_task, comp_arg_raw)
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{
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__prof;
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struct shader_compile_task_arg *comp_arg = (struct shader_compile_task_arg *)comp_arg_raw;
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struct dx12_pipeline *pipeline = comp_arg->pipeline;
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struct pipeline *pipeline = comp_arg->pipeline;
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struct string shader_name = string_from_cstr_no_limit(pipeline->desc.shader);
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enum shader_compile_task_kind kind = comp_arg->kind;
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struct resource *src_res = comp_arg->src_res;
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@ -775,17 +773,17 @@ INTERNAL WORK_TASK_FUNC_DEF(shader_compile_task, comp_arg_raw)
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* ========================== */
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struct pipeline_load_task_arg {
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struct dx12_pipeline *pipeline;
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struct dx12_pipeline_result *result;
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struct pipeline *pipeline;
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struct pipeline_result *result;
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};
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INTERNAL WORK_TASK_FUNC_DEF(pipeline_load_task, load_arg_raw)
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{
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__prof;
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struct pipeline_load_task_arg *load_arg = (struct pipeline_load_task_arg *)load_arg_raw;
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struct dx12_pipeline *pipeline = load_arg->pipeline;
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struct dx12_pipeline_desc desc = pipeline->desc;
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struct dx12_pipeline_result *result = load_arg->result;
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struct pipeline *pipeline = load_arg->pipeline;
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struct pipeline_desc desc = pipeline->desc;
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struct pipeline_result *result = load_arg->result;
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struct arena_temp scratch = scratch_begin_no_conflict();
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{
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@ -804,19 +802,19 @@ INTERNAL WORK_TASK_FUNC_DEF(pipeline_load_task, load_arg_raw)
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ps.src_res = &src_res;
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ps.pipeline = pipeline;
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/* Compile shaders */
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struct work_slate ws = work_slate_begin();
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if (desc.flags & DX12_PIPELINE_DESC_FLAG_VS) {
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if (desc.flags & PIPELINE_DESC_FLAG_VS) {
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work_slate_push_task(&ws, shader_compile_task, &vs);
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}
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if (desc.flags & DX12_PIPELINE_DESC_FLAG_PS) {
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if (desc.flags & PIPELINE_DESC_FLAG_PS) {
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work_slate_push_task(&ws, shader_compile_task, &ps);
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}
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struct work_handle work = work_slate_end_and_help(&ws, WORK_PRIORITY_NORMAL);
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work_wait(work);
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b32 success = vs.success && ps.success;
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/* FIXME: Validate root signature blob exists in bytecode */
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b32 success = vs.success && ps.success;
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/* Create PSO */
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ID3D12PipelineState *pso = NULL;
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@ -922,19 +920,18 @@ INTERNAL WORK_TASK_FUNC_DEF(pipeline_load_task, load_arg_raw)
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scratch_end(scratch);
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}
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INTERNAL struct dx12_pipeline_result *pipeline_alloc_from_descs(struct arena *arena, u64 num_pipelines, struct dx12_pipeline_desc *descs)
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INTERNAL struct pipeline_result *pipeline_alloc_from_descs(struct arena *arena, u64 num_pipelines, struct pipeline_desc *descs)
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{
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__prof;
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struct dx12_pipeline_result *results = arena_push_array(arena, struct dx12_pipeline_result, num_pipelines);
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struct pipeline_result *results = arena_push_array(arena, struct pipeline_result, num_pipelines);
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struct pipeline_load_task_arg *task_args = arena_push_array(arena, struct pipeline_load_task_arg, num_pipelines);
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struct sys_mutex arena_mutex = sys_mutex_alloc();
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/* Create & dispatch work */
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/* Load pipelines */
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struct work_slate ws = work_slate_begin();
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for (u64 i = 0; i < num_pipelines; ++i) {
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struct dx12_pipeline_result *result = &results[i];
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struct pipeline_result *result = &results[i];
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struct dx12_pipeline *pipeline = &results->pipeline;
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struct pipeline *pipeline = &results->pipeline;
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pipeline->desc = descs[i];
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struct pipeline_load_task_arg *arg = &task_args[i];
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@ -946,11 +943,10 @@ INTERNAL struct dx12_pipeline_result *pipeline_alloc_from_descs(struct arena *ar
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struct work_handle work = work_slate_end_and_help(&ws, WORK_PRIORITY_NORMAL);
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work_wait(work);
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sys_mutex_release(&arena_mutex);
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return results;
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}
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INTERNAL void dx12_pipeline_release(struct dx12_pipeline *pipeline)
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INTERNAL void pipeline_release(struct pipeline *pipeline)
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{
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__prof;
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if (pipeline->pso) {
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@ -959,21 +955,26 @@ INTERNAL void dx12_pipeline_release(struct dx12_pipeline *pipeline)
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}
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/* ========================== *
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* Texture
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* Buffer
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* ========================== */
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INTERNAL void dx12_texture_release(struct dx12_texture *t)
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INTERNAL void dx12_buffer_release(struct dx12_buffer *t)
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{
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(UNUSED)t;
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}
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/* ========================== *
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* Texture
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* ========================== */
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struct gpu_handle gpu_texture_alloc(enum gpu_texture_format format, u32 flags, struct v2i32 size, void *initial_data)
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{
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(UNUSED)format;
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(UNUSED)flags;
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(UNUSED)size;
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(UNUSED)initial_data;
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struct dx12_texture *t = NULL;
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struct dx12_buffer *t = NULL;
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return handle_alloc(DX12_HANDLE_KIND_TEXTURE, t);
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}
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